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PI7C8148A
2-Port PCI-to-PCI Bridge
REVISION 1.04
3545 North First Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) Fax: 408-435-1100 Email: solutions@pericom.com Internet: http://www.pericom.com
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
LIFE SUPPORT POLICY Pericom Semiconductor Corporation's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC. 1) Life support devices or system are devices or systems which: a) Are intended for surgical implant into the body or b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2) A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
REVISION HISTORY
DATE 11-13-2003 03-25-2004 04-26-2004 05-10-2004 REVISION NUMBER 0.01 0.02 0.03 1.00 DESCRIPTION First Draft of Datasheet First release of preliminary datasheet Revisions/changes to GPIO and EEPROM references Revisions to EEPROM references Revisions to ordering information, correction to package codes Further modifications to EEPROM information Changed type for "Data Select" in 15.2.41 from RO to RW Added power consumptions data in section 16.6 Added TDELAY data in sections 16.4 and 16.5 Revised descriptions in sections 15.2.39, 15.2.47, and 15.2.48. Added VPD register descriptions (section 15.2.50 - 15.2.53)
05-17-2004 05-19-2004 06-11-2004 06-14-2004
1.01 1.02 1.03 1.04
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
TABLE OF CONTENTS
1 SIGNAL DEFINITIONS.............................................................................................................................13 1.1 SIGNAL TYPES....................................................................................................................................13 1.2 SIGNALS ..............................................................................................................................................13 1.2.1 PRIMARY BUS INTERFACE SIGNALS ...................................................................................13 1.2.2 SECONDARY BUS INTERFACE SIGNALS .............................................................................14 1.2.3 CLOCK SIGNALS ........................................................................................................................16 1.2.4 MISCELLANEOUS SIGNALS ....................................................................................................16 1.2.5 GENERAL PURPOSE I/O INTERFACE SIGNALS .................................................................17 1.2.6 POWER AND GROUND..............................................................................................................17 1.3 PIN LIST - 160-PIN LFBGA.................................................................................................................18 2 PCI BUS OPERATION...............................................................................................................................19 2.1 TYPES OF TRANSACTIONS ..............................................................................................................19 2.2 SINGLE ADDRESS PHASE.................................................................................................................20 2.3 DEVICE SELECT (DEVSEL#) GENERATION ..................................................................................20 2.4 DATA PHASE.......................................................................................................................................20 2.5 WRITE TRANSACTIONS....................................................................................................................20 2.5.1 MEMORY WRITE TRANSACTIONS.........................................................................................21 2.5.2 MEMORY WRITE AND INVALIDATE .....................................................................................22 2.5.3 DELAYED WRITE TRANSACTIONS ........................................................................................22 2.5.4 WRITE TRANSACTION BOUNDARIES...................................................................................23 2.5.5 BUFFERING MULTIPLE WRITE TRANSACTIONS..............................................................23 2.5.6 FAST BACK-TO-BACK TRANSACTIONS ................................................................................23 2.6 READ TRANSACTIONS .....................................................................................................................24 2.6.1 PREFETCHABLE READ TRANSACTIONS .............................................................................24 2.6.2 DYNAMIC PREFETCHING CONTROL....................................................................................24 2.6.3 NON-PREFETCHABLE READ TRANSACTIONS ...................................................................24 2.6.4 READ PREFETCH ADDRESS BOUNDARIES ........................................................................25 2.6.5 DELAYED READ REQUESTS ...................................................................................................25 2.6.6 DELAYED READ COMPLETION WITH TARGET .................................................................26 2.6.7 DELAYED READ COMPLETION ON INITIATOR BUS.........................................................26 2.6.8 FAST BACK-TO-BACK READ TRANSACTIONS ....................................................................27 2.7 CONFIGURATION TRANSACTIONS................................................................................................27 2.7.1 TYPE 0 ACCESS TO PI7C8148A................................................................................................28 2.7.2 TYPE 1 TO TYPE 0 CONVERSION ...........................................................................................28 2.7.3 TYPE 1 TO TYPE 1 FORWARDING ..........................................................................................29 2.7.4 SPECIAL CYCLES.......................................................................................................................30 2.8 TRANSACTION TERMINATION.......................................................................................................30 2.8.1 MASTER TERMINATION INITIATED BY PI7C8148A ..........................................................31 2.8.2 MASTER ABORT RECEIVED BY PI7C8148A .........................................................................32 2.8.3 TARGET TERMINATION RECEIVED BY PI7C8148A ...........................................................32 2.8.4 TARGET TERMINATION INITIATED BY PI7C8148A...........................................................34 3 ADDRESS DECODING..............................................................................................................................36 3.1 ADDRESS RANGES ............................................................................................................................36 3.2 I/O ADDRESS DECODING..................................................................................................................36 3.2.1 I/O BASE AND LIMIT ADDRESS REGISTER .........................................................................37 3.2.2 ISA MODE ....................................................................................................................................37 3.3 MEMORY ADDRESS DECODING .....................................................................................................38 3.3.1 MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ..................................38 3.3.2 PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ..........................39 Page 5 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 3.4 VGA SUPPORT ....................................................................................................................................40 3.4.1 VGA MODE ..................................................................................................................................40 3.4.2 VGA SNOOP MODE ....................................................................................................................40 4 TRANSACTION ORDERING ...................................................................................................................41 4.1 4.2 4.3 4.4 5 TRANSACTIONS GOVERNED BY ORDERING RULES .................................................................41 GENERAL ORDERING GUIDELINES ...............................................................................................42 ORDERING RULES .............................................................................................................................43 DATA SYNCHRONIZATION .............................................................................................................44
ERROR HANDLING ..................................................................................................................................44 5.1 ADDRESS PARITY ERRORS..............................................................................................................44 5.2 DATA PARITY ERRORS.....................................................................................................................45 5.2.1 CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE ...................45 5.2.2 READ TRANSACTIONS .............................................................................................................45 5.2.3 DELAYED WRITE TRANSACTIONS ........................................................................................46 5.2.4 POSTED WRITE TRANSACTIONS ...........................................................................................48 5.3 DATA PARITY ERROR REPORTING SUMMARY...........................................................................49 5.4 SYSTEM ERROR (SERR#) REPORTING ...........................................................................................52
6
PCI BUS ARBITRATION ..........................................................................................................................53 6.1 PRIMARY PCI BUS ARBITRATION ..................................................................................................53 6.2 SECONDARY PCI BUS ARBITRATION............................................................................................53 6.2.1 PREEMPTION .............................................................................................................................53 6.2.2 BUS PARKING .............................................................................................................................54
7
CLOCKS ......................................................................................................................................................54 7.1 7.2 7.3 PRIMARY CLOCK INPUTS ................................................................................................................54 SECONDARY CLOCK OUTPUTS ......................................................................................................54 PCI CLOCKRUN ..................................................................................................................................54 GPIO CONTROL REGISTERS ............................................................................................................55
8 9
GENERAL PURPOSE I/O INTERFACE.................................................................................................55 8.1 EEPROM INTERFACE .............................................................................................................................55 9.1 AUTO MODE EEPROM ACCESS .......................................................................................................55 9.2 EEPROM MODE AT RESET................................................................................................................56 9.3 EEPROM DATA STRUCTURE ...........................................................................................................56 9.4 EEPROM SPACE ADDRESS MAP......................................................................................................56 9.4.1 EEPROM CONTENT...................................................................................................................56
10 11 12 12.1 12.2 12.3 13 13.1 13.2
COMPACT PCI HOT SWAP.................................................................................................................58 PCI POWER MANAGEMENT .............................................................................................................58 RESET ......................................................................................................................................................59 PRIMARY INTERFACE RESET..........................................................................................................59 SECONDARY INTERFACE RESET ...................................................................................................59 CHIP RESET .........................................................................................................................................60 SUPPORTED COMMANDS ..................................................................................................................60 PRIMARY INTERFACE ......................................................................................................................60 SECONDARY INTERFACE ................................................................................................................61
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 14 BRIDGE BEHAVIOR.............................................................................................................................62
14.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES.........................................................................62 14.2 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) ..............................................63 14.2.1 MASTER ABORT .........................................................................................................................63 14.2.2 PARITY AND ERROR REPORTING .........................................................................................63 14.2.3 REPORTING PARITY ERRORS.................................................................................................63 14.2.4 SECONDARY IDSEL MAPPING................................................................................................63 15 CONFIGURATION REGISTERS.........................................................................................................64 15.1 REGISTER TYPES ...............................................................................................................................64 15.2 CONFIGURATION REGISTER...........................................................................................................64 15.2.1 VENDOR ID REGISTER - OFFSET 00h ..................................................................................65 15.2.2 DEVICE ID REGISTER - OFFSET 00h....................................................................................65 15.2.3 COMMAND REGISTER - OFFSET 04h ...................................................................................65 15.2.4 PRIMARY STATUS REGISTER - OFFSET 04h ......................................................................66 15.2.5 REVISION ID REGISTER - OFFSET 08h................................................................................67 15.2.6 CLASS CODE REGISTER - OFFSET 08h ................................................................................67 15.2.7 CACHE LINE REGISTER - OFFSET 0Ch ...............................................................................67 15.2.8 PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch.....................................................67 15.2.9 HEADER TYPE REGISTER - OFFSET 0Ch ............................................................................67 15.2.10 PRIMARY BUS NUMBER REGISTER - OFFSET 18h .......................................................67 15.2.11 SECONDARY BUS NUMBER REGISTER - OFFSET 18h .................................................68 15.2.12 SUBORDINATE BUS NUMBER REGISTER - OFFSET 18h .............................................68 15.2.13 SECONDARY LATENCY TIMER REGISTER - OFFSET 18h ...........................................68 15.2.14 I/O BASE ADDRESS REGISTER - OFFSET 1Ch................................................................68 15.2.15 I/O LIMIT ADDRESS REGISTER - OFFSET 1Ch ..............................................................68 15.2.16 SECONDARY STATUS REGISTER - OFFSET 1Ch............................................................69 15.2.17 MEMORY BASE ADDRESS REGISTER - OFFSET 20h ....................................................69 15.2.18 MEMORY LIMIT ADDRESS REGISTER - OFFSET 20h ...................................................70 15.2.19 PREFETCHABLE MEMORY BASE ADDRESS REGISTER - OFFSET 24h....................70 15.2.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER - OFFSET 24h ..................70 15.2.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER - OFFSET 28h ...................................................................................................................................................70 15.2.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER - OFFSET 2Ch ...................................................................................................................................................71 15.2.23 I/O BASE ADDRESS UPPER 16-BITS REGISTER - OFFSET 30h ...................................71 15.2.24 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER - OFFSET 30h ..................................71 15.2.25 CAPABILITY POINTER REGISTER - OFFSET 34h ..........................................................71 15.2.26 INTERRUPT LINE REGISTER - OFFSET 3Ch ..................................................................71 15.2.27 INTERRUPT PIN REGISTER - OFFSET 3Ch .....................................................................71 15.2.28 BRIDGE CONTROL REGISTER - OFFSET 3Ch ................................................................72 15.2.29 DIAGNOSTIC/CHIP CONTROL REGISTER - OFFSET 40h .............................................73 15.2.30 ARBITER CONTROL REGISTER - OFFSET 40h ...............................................................74 15.2.31 EXTENDED CHIP CONTROL REGISTER - OFFSET 48h ................................................74 15.2.32 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER - OFFSET 4Ch ..75 15.2.33 P_SERR# EVENT DISABLE REGISTER - OFFSET 64h ...................................................76 15.2.34 SECONDARY CLOCK CONTROL REGISTER - OFFSET 68h ..........................................77 15.2.35 P_SERR# STATUS REGISTER - OFFSET 68h....................................................................77 15.2.36 CLKRUN REGISTER - OFFSET 6Ch ...................................................................................78 15.2.37 PORT OPTION REGISTER - OFFSET 74h..........................................................................78 15.2.38 CAPABILITY ID REGISTER - OFFSET 80h .......................................................................80 15.2.39 NEXT ITEM POINTER REGISTER - OFFSET 80h ............................................................80 15.2.40 POWER MANAGEMENT CAPABILITIES REGISTER - OFFSET 80h ............................81 Page 7 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 15.2.41 15.2.42 15.2.43 15.2.44 15.2.45 15.2.46 15.2.47 15.2.48 15.2.49 15.2.50 15.2.51 15.2.52 15.2.53 15.2.54 15.2.55 15.2.56 15.2.57 15.2.58 15.2.59 15.2.60 15.2.61 16 16.1 16.2 16.3 16.4 16.5 16.6 17 17.1 17.2 POWER MANAGEMENT DATA REGISTER - OFFSET 84h.............................................81 PPB SUPPORT EXTENSIONS - OFFSET 84h ....................................................................81 DATA REGISTER - OFFSET 84h..........................................................................................81 PRIMARY MASTER TIMEOUT COUNTER REGISTER - OFFSET 88h..........................82 SECONDARY MASTER TIMEOUT COUNTER REGISTER - OFFSET 88h ....................82 CAPABILITY ID REGISTER - OFFSET 90h .......................................................................82 NEXT ITEM POINTER REGISTER - OFFSET 90h ............................................................82 HOT SWAP CAPABILITY STRUCTURE REGISTER - OFFSET 90h ...............................82 HOT SWAP SWITCH REGISTER - OFFSET 94h ...............................................................83 VPD CAPABILITY ID REGISTER - OFFSET A0h..............................................................83 NEXT ITEM POINTER REGISTER - OFFSET A0h ...........................................................83 VPD REGISTER - OFFSET A0h ...........................................................................................83 VPD DATA REGISTER - OFFSET A4h................................................................................84 MISCELLANEOUS CONTROL REGISTER - OFFSET C0h ..............................................84 GPIO CONTROL REGISTER - OFFSET C4h ......................................................................84 EEPROM CONTROL REGISTER - OFFSET C8h ...............................................................85 EEPROM ADDRESS REGISTER - OFFSET C8h................................................................85 EEPROM DATA REGISTER - OFFSET C8h .......................................................................86 EEPROM TEST REGISTER - OFFSET CCh .......................................................................86 SUBSYSTEM VENDOR ID REGISTER - OFFSET F0h .....................................................86 SUBSYSTEM ID - OFFSET F0h............................................................................................87
ELECTRICAL AND TIMING SPECIFICATIONS ............................................................................87 MAXIMUM RATINGS.........................................................................................................................87 DC SPECIFICATIONS .........................................................................................................................87 AC SPECIFICATIONS .........................................................................................................................88 66MHZ TIMING ...................................................................................................................................89 33MHZ TIMING ...................................................................................................................................89 POWER CONSUMPTION....................................................................................................................89 PACKAGE INFORMATION.................................................................................................................90 160-PIN LFBGA PACKAGE OUTLINE ..............................................................................................90 PART NUMBER ORDERING INFORMATION .................................................................................90
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
LIST OF TABLES
TABLE 2-1. PCI TRANSACTIONS.............................................................................................................................19 TABLE 2-2. WRITE TRANSACTION FORWARDING ..................................................................................................21 TABLE 2-3. WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES ..............................................................23 TABLE 2-4. READ PREFETCH ADDRESS BOUNDARIES............................................................................................25 TABLE 2-5. READ TRANSACTION PREFETCHING ....................................................................................................25 TABLE 2-6. DEVICE NUMBER TO IDSEL S_AD PIN MAPPING...............................................................................29 TABLE 2-7. DELAYED WRITE TARGET TERMINATION RESPONSE ..........................................................................33 TABLE 2-8. RESPONSE TO POSTED WRITE TARGET TERMINATION ........................................................................33 TABLE 2-9. RESPONSE TO DELAYED READ TARGET TERMINATION.......................................................................34 TABLE 4-1. SUMMARY OF TRANSACTION ORDERING.............................................................................................43 TABLE 5-1. SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT ....................................................49 TABLE 5-2. SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT ......................................................49 TABLE 5-3. SETTING PRIMARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT ..................................50 TABLE 5-4. SETTING SECONDARY INTERFACE MASTER DATA PARITY ERROR DETECTED BIT..............................50 TABLE 5-5. ASSERTION OF P_PERR# ....................................................................................................................51 TABLE 5-6. ASSERTION OF S_PERR# ....................................................................................................................51 TABLE 5-7. ASSERTION OF P_SERR# FOR DATA PARITY ERRORS ........................................................................52 TABLE 11-1. POWER MANAGEMENT TRANSITIONS................................................................................................59
LIST OF FIGURES
FIGURE 16-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS .........................................................................88 FIGURE 17-1 160-PIN LFBGA PACKAGE OUTLINE .................................................................................................90
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
INTRODUCTION
Product Description
The PI7C8148A is Pericom Semiconductor's PCI-to-PCI Bridge, designed to be fully compliant with the 32-bit, 66MHz implementation of the PCI Local Bus Specification, Revision 2.2. The PI7C8148A supports synchronous bus transactions between devices on the Primary Bus and the Secondary Buses operating up to 66MHz. Both primary and secondary buses must operate at the same frequency. The primary and secondary buses can also operate in concurrent mode, resulting in added increase in system performance.
Product Features
! ! ! 32-bit Primary and Secondary Ports run up to 66MHz Compliant with the PCI Local Bus Specification, Revision 2.2 Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1. - All I/O and memory commands - Type 1 to Type 0 configuration conversion - Type 1 to Type 1 configuration forwarding - Type 1 configuration write to special cycle conversion Compliant with the Advanced Configuration Power Interface (ACPI) Compliant with the PCI Power Management Specification, Revision 1.1 Compliant with the PCI Mobile Design Guide, Revision 1.1 Provides internal arbitration for four secondary bus masters - Programmable 2-level priority arbiter Supports serial EEPROM interface for register auto-load and VPD access Supports posted write buffers in all directions Dynamic Prefetching Control Four 128 byte FIFO's for delay transactions Two 128 byte FIFO's for posted memory transactions Enhanced address decoding 32-bit I/O address range 32-bit memory-mapped I/O address range 64-bit prefetchable address range Extended commercial temperature range 0C to 85C 3.3V and 5V signaling 160-pin LFBGA package
! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
1
1.1
SIGNAL DEFINITIONS
SIGNAL TYPES
SIGNAL TYPE I O P TS STS OD DESCRIPTION Input only Output only Power Tri-state bi-directional Sustained tri-state. Active LOW signal must be pulled HIGH for 1 cycle when deasserting. Open Drain
1.2
SIGNALS
Signals that end with "#" are active LOW.
1.2.1
PRIMARY BUS INTERFACE SIGNALS
Name P_AD[31:0] Pin Number P10, N10, M10, P11, N11, M11, P12, N12, M14, L12, L13, L14, K12, K13, K14, J12, E14, E13, E12, D14, D13, D12, C13, B14, B12, A12, C11, B11, A11, C10, A10, C9 P14, J13, F12, A13 Type TS Description Primary Address / Data: Multiplexed address and data bus. Address is indicated by P_FRAME# assertion. Write data is stable and valid when P_IRDY# is asserted and read data is stable and valid when P_TRDY# is asserted. Data is transferred on rising clock edges when both P_IRDY# and P_TRDY# are asserted. During bus idle, PI7C8148A drives P_AD to a valid logic level when P_GNT# is asserted. Primary Command/Byte Enables: Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins. After that, the initiator drives the byte enables during data phases. During bus idle, PI7C8148A drives P_CBE#[3:0] to a valid logic level when P_GNT# is asserted. Primary Parity. Parity is even across P_AD[31:0], P_CBE#[3:0], and P_PAR (i.e. an even number of 1's). P_PAR is an input and is valid and stable one cycle after the address phase (indicated by assertion of P_FRAME#) for address parity. For write data phases, P_PAR is an input and is valid one clock after P_IRDY# is asserted. For read data phase, P_PAR is an output and is valid one clock after P_TRDY# is asserted. Signal P_PAR is tri-stated one cycle after the P_AD lines are tri-stated. During bus idle, PI7C8148A drives P_PAR to a valid logic level when P_GNT# is asserted. Primary FRAME (Active LOW). Driven by the initiator of a transaction to indicate the beginning and duration of an access. The de-assertion of P_FRAME# indicates the final data phase requested by the initiator. Before being tri-stated, it is driven to a de-asserted state for one cycle. Primary IRDY (Active LOW). Driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not deasserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle.
P_CBE#[3:0]
TS
P_PAR
F13
TS
P_FRAME#
J14
STS
P_IRDY#
H12
STS
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name P_TRDY# Pin Number H13 Type STS Description Primary TRDY (Active LOW). Driven by the target of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not deasserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary Device Select (Active LOW). Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C8148A waits for the assertion of this signal within 5 cycles of P_FRAME# assertion; otherwise, terminate with master abort. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary STOP (Active LOW). Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before tri-stated, it is driven to a de-asserted state for one cycle. Primary ID Select. Used as a chip select line for Type 0 configuration access to PI7C8148A configuration space. Primary Parity Error (Active LOW). Asserted when a data parity error is detected for data received on the primary interface. Before being tri-stated, it is driven to a de-asserted state for one cycle. Primary System Error (Active LOW). Can be driven LOW by any device to indicate a system error condition. PI7C8148A drives this pin on: ! Address parity error ! Posted write data parity error on target bus ! Secondary S_SERR# asserted ! Master abort during posted write transaction ! Target abort during posted write transaction ! Posted write transaction discarded ! Delayed write request discarded ! Delayed read request discarded ! Delayed transaction master timeout This signal requires an external pull-up resistor for proper operation. Primary Request (Active LOW): This is asserted by PI7C8148A to indicate that it wants to start a transaction on the primary bus. PI7C8148A de-asserts this pin for at least 2 PCI clock cycles before asserting it again. Primary Grant (Active LOW): When asserted, PI7C8148A can access the primary bus. During idle and P_GNT# asserted, PI7C8148A will drive P_AD, P_CBE, and P_PAR to valid logic levels. Primary RESET (Active LOW): When P_RST# is active, all PCI signals should be asynchronously tri-stated.
P_DEVSEL#
H14
STS
P_STOP#
G14
STS
P_IDSEL P_PERR#
N14 G12
I STS
P_SERR#
F14
OD
P_REQ#
M9
TS
P_GNT#
N9
I
P_RST#
P8
I
1.2.2
SECONDARY BUS INTERFACE SIGNALS
Name S_AD[31:0] Pin Number M1, L3, L2, L1, K3, K1, J3, J2, H3, H2, H1, G1, G2, G3, F1, F2, A3, C4, A4, C5, B5, A5, C6, B6, C7, B7, A7, A8, B8, C8, A9, B9 J1, F3, A2, A6 Type TS Description Secondary Address/Data: Multiplexed address and data bus. Address is indicated by S_FRAME# assertion. Write data is stable and valid when S_IRDY# is asserted and read data is stable and valid when S_TRDY# is asserted. Data is transferred on rising clock edges when both S_IRDY# and S_TRDY# are asserted. During bus idle, PI7C8148A drives S_AD to a valid logic level when S_GNT# is asserted respectively. Secondary Command/Byte Enables: Multiplexed command field and byte enable field. During address phase, the initiator drives the transaction type on these pins. The initiator then drives the byte enables during data phases. During bus idle, PI7C8148A drives S_CBE#[3:0] to a valid logic level when the internal grant is asserted.
S_CBE#[3:0]
TS
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Name S_PAR Pin Number B1 Type TS Description Secondary Parity: Parity is even across S_AD[31:0], S_CBE#[3:0], and S_PAR (i.e. an even number of 1's). S_PAR is an input and is valid and stable one cycle after the address phase (indicated by assertion of S_FRAME#) for address parity. For write data phases, S_PAR is an input and is valid one clock after S_IRDY# is asserted. For read data phase, S_PAR is an output and is valid one clock after S_TRDY# is asserted. Signal S_PAR is tri-stated one cycle after the S_AD lines are tri-stated. During bus idle, PI7C8148A drives S_PAR to a valid logic level when the internal grant is asserted. Secondary FRAME (Active LOW): Driven by the initiator of a transaction to indicate the beginning and duration of an access. The de-assertion of S_FRAME# indicates the final data phase requested by the initiator. Before being tri-stated, it is driven to a de-asserted state for one cycle. Secondary IRDY (Active LOW): Driven by the initiator of a transaction to indicate its ability to complete current data phase on the secondary side. Once asserted in a data phase, it is not deasserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Secondary TRDY (Active LOW): Driven by the target of a transaction to indicate its ability to complete current data phase on the secondary side. Once asserted in a data phase, it is not deasserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Secondary Device Select (Active LOW): Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C8148A waits for the assertion of this signal within 5 cycles of S_FRAME# assertion; otherwise, terminate with master abort. Before tri-stated, it is driven to a de-asserted state for one cycle. Secondary STOP (Active LOW): Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before tri-stated, it is driven to a de-asserted state for one cycle. Secondary Parity Error (Active LOW): Asserted when a data parity error is detected for data received on the secondary interface. Before being tri-stated, it is driven to a de-asserted state for one cycle. Secondary System Error (Active LOW): Can be driven LOW by any device to indicate a system error condition. Secondary Request (Active LOW): This is asserted by an external device to indicate that it wants to start a transaction on the secondary bus. The input is externally pulled up through a resistor to VDD. Secondary Grant (Active LOW): PI7C8148A asserts these pins to allow external masters to access the secondary bus. PI7C8148A de-asserts these pins for at least 2 PCI clock cycles before asserting it again. During idle and S_GNT# deasserted, PI7C8148A will drive S_AD, S_CBE, and S_PAR. Secondary RESET (Active LOW): Asserted when any of the following conditions are met: 1. Signal P_RST# is asserted. 2. Secondary reset bit in bridge control register in configuration space is set. When asserted, all control signals are tri-stated and zeroes are driven on S_AD, S_CBE, and S_PAR.
S_FRAME#
E2
STS
S_IRDY#
E3
STS
S_TRDY#
D1
STS
S_DEVSEL#
D2
STS
S_STOP#
D3
STS
S_PERR#
C1
STS
S_SERR# S_REQ#[3:0]
C2 P2, P1, N1, M2
I I
S_GNT#[3:0]
N4, M4, P3, N3
TS
S_RST#
P4
O
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1.2.3
CLOCK SIGNALS
Name P_CLK S_CLKIN S_CLKOUT[4:0] Pin Number M8 M5 M7, P6, N6, M6, P5 Type I I O Description Primary Clock Input: Provides timing for all transactions on the primary interface. Secondary Clock Input: Provides timing for all transactions on the secondary interface. Secondary Clock Output: Provides secondary clocks phase synchronous with the P_CLK. One of the clock outputs must be fed back to S_CLKIN. Unused outputs may be disabled by: 1. Writing the secondary clock disable bits in the configuration space 2. Terminating them electrically. Primary Clock Run: Allows main system to stop the primary clock based on the specifications in the PCI Mobile Design Guide, Revision 1.0. If unused, this pin should be tied to ground to signify that P_CLK is always running. Secondary Clock Run: Allows main system to slow down or stop the secondary clock and is controlled by the primary or bit[4] offset 6Fh. If the secondary devices do not support CLKRUN, this pin should be pulled LOW by a 300 ohm resistor.
P_CLKRUN#
A14
TS
S_CLKRUN#
B3
TS
1.2.4
MISCELLANEOUS SIGNALS
Name ENUM# LOO Pin Number B4 B10 Type O I/O Description Hot Swap Status Indicator: The output of ENUM# indicates to the system that an insertion has occurred or that an extraction is about to occur. Hot Swap LED: The output of this pin lights an LED to indicate insertion or removal ready status. This pin may also be used as a input or detect pin. Every 500us, the pin tri-states for 8 primary PCI clock cycles to sample the status. Hot Swap Switch. When driven LOW, this signal indicates that the board ejector handle indicates an insertion or impending extraction of a board. EEPROM Clock: Clock signal to the EEPROM interface EEPROM Data: Serial data interface to the EEPROM Primary I/O Voltage: This pin is used to determine either 3.3V or 5V signaling on the primary bus. P_VIO must be tied to 3.3V only when all devices on the primary bus use 3.3V signaling. Otherwise, P_VIO is tied to 5V. Secondary I/O Voltage: This pin is used to determine either 3.3V or 5V signaling on the secondary bus. S_VIO must be tied to 3.3V only when all devices on the secondary bus use 3.3V signaling. Otherwise, S_VIO is tied to 5V. Full-Scan Test Mode Enable: For normal operation, pull SCAN_TM# to HIGH. Manufacturing test pin. Full-Scan Enable Control: For normal operation, SCAN_TM# should be pulled HIGH and SCAN_EN becomes an output with logic 0. Manufacturing test pin. Bus/Power Clock Control Management Pin: When this pin is tied HIGH and the PI7C8148A is placed in the D3HOT power state, it enables the PI7C8148A to place the secondary bus in the B2 power state. The secondary clocks are disabled and driven to 0. When this pin is tied LOW, there is no effect on the secondary bus clocks when the PI7C8148A enters the D3HOT power state.
EJECT EECLK EEPD P_VIO
C14 G13 E1 P9
I O TS I
S_VIO
N5
I
SCAN_TM# SCAN_EN BPCEE
P7 N7 A1
I I/O I
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1.2.5
GENERAL PURPOSE I/O INTERFACE SIGNALS
Name GPIO[3:0] Pin Number M13, P13, N8, K2 Type TS Description General Purpose I/O Data Pins: The 4 general-purpose signals are programmable as either input-only or bi-directional signals by writing the GPIO output enable control register in the configuration space.
1.2.6
POWER AND GROUND
Name VDD Pin Number D6, D7, D8, D9, F4, F11, G4, G11, H4, H11, J4, J11, L6, L7, L8 ,L9 B2, B13, C3, C12, D4, D5, D10, D11, E4, E11, K4, K11, L4, L5, L10, L11, M3, M12, N2, N13 Type P Description Power: 3.3V power
VSS
P
Ground
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1.3
PIN LIST - 160-PIN LFBGA
Pin Number A1 A3 A5 A7 A9 A11 A13 B1 B3 B5 B7 B9 B11 B13 C1 C3 C5 C7 C9 C11 C13 D1 D3 D5 D7 D9 D11 D13 E1 E3 E11 E13 F1 F3 F11 F13 G1 G3 G11 G13 H1 H3 H11 H13 J1 J3 J11 J13 K1 K3 K11 K13 L1 L3 L5 L7 L9 L11 L13 Name BPCEE S_AD[15] S_AD[10] S_AD[5] S_AD[1] P_AD[3] P_CBE#[0] S_PAR S_CLKRUN# S_AD[11] S_AD[6] S_AD[0] P_AD[4] VSS S_PERR# VSS S_AD[12] S_AD[7] P_AD[0] P_AD[5] P_AD[9] S_TRDY# S_STOP# VSS VDD VDD VSS P_AD[11] EEPD S_IRDY# VSS P_AD[14] S_AD[17] S_CBE#[2] VDD P_PAR S_AD[20] S_AD[18] VDD EECLK S_AD[21] S_AD[23] VDD P_TRDY# S_CBE#[3] S_AD[25] VDD P_CBE#[2] S_AD[26] S_AD[27] VSS P_AD[18] S_AD[28] S_AD[30] VSS VDD VDD VSS P_AD[21] Type I TS TS TS TS TS TS TS TS TS TS TS TS P STS P TS TS TS TS TS STS STS P P P P TS TS STS P TS TS TS P TS TS TS P O TS TS P STS TS TS P TS TS TS P TS TS TS P P P P TS Pin Number A2 A4 A6 A8 A10 A12 A14 B2 B4 B6 B8 B10 B12 B14 C2 C4 C6 C8 C10 C12 C14 D2 D4 D6 D8 D10 D12 D14 E2 E4 E12 E14 F2 F4 F12 F14 G2 G4 G12 G14 H2 H4 H12 H14 J2 J4 J12 J14 K2 K4 K12 K14 L2 L4 L6 L8 L10 L12 L14 Name S_CBE#[1] S_AD[13] S_CBE#[0] S_AD[4] P_AD[1] P_AD[6] P_CLKRUN# VSS ENUM# S_AD[8] S_AD[3] LOO P_AD[7] P_AD[8] S_SERR# S_AD[14] S_AD[9] S_AD[2] P_AD[2] VSS EJECT S_DEVSEL# VSS VDD VDD VSS P_AD[10] P_AD[12] S_FRAME# VSS P_AD[13] P_AD[15] S_AD[16] VDD P_CBE#[1] P_SERR# S_AD[19] VDD P_PERR# P_STOP# S_AD[22] VDD P_IRDY# P_DEVSEL# S_AD[24] VDD P_AD[16] P_FRAME# GPIO[0] VSS P_AD[19] P_AD[17] S_AD[29] VSS VDD VDD VSS P_AD[22] P_AD[20] Type TS TS TS TS TS TS TS P O TS TS I/O TS TS I TS TS TS TS P I STS P P P P TS TS STS P TS TS TS P TS OD TS P G12 I TS P STS STS TS P TS STS TS P TS TS TS P P P P TS TS
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Pin Number M1 M3 M5 M7 M9 M11 M13 N1 N3 N5 N7 N9 N11 N13 P1 P3 P5 P7 P9 P11 P13 Name S_AD[31] VSS S_CLKIN S_CLKOUT[4] P_REQ# P_AD[26] GPIO[3] S_REQ#[1] S_GNT#[0] S_VIO SCAN_EN P_GNT# P_AD[27] VSS S_REQ#[2] S_GNT#[1] S_CLKOUT[0] SCAN_TM# P_VIO P_AD[28] GPIO[2] Type TS P I O TS TS TS I TS I I/O I TS P I TS O I I TS TS Pin Number M2 M4 M6 M8 M10 M12 M14 N2 N4 N6 N8 N10 N12 N14 P2 P4 P6 P8 P10 P12 P14 Name S_REQ#[0] S_GNT#[2] S_CLKOUT[1] P_CLK P_AD[29] VSS P_AD[23] VSS S_GNT#[3] S_CLKOUT[2] GPIO[1] P_AD[30] P_AD[24] P_IDSEL S_REQ#[3] S_RST# S_CLKOUT[3] P_RST# P_AD[31] P_AD[25] P_CBE#[3] Type I TS O I TS P TS P TS O TS TS TS I I O O I TS TS TS
2
PCI BUS OPERATION
This Chapter offers information about PCI transactions, transaction forwarding across the bridge, and transaction termination. The bridge has two 128-byte FIFO's for buffering of upstream and downstream transactions. These hold addresses, data, commands, and byte enables that are used for write transactions. The bridge also has an additional four 128-byte FIFO's that hold addresses, data, commands, and byte enables for read transactions.
2.1
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by the bridge. Table 2-1 lists the command code and name of each PCI transaction. The Master and Target columns indicate support for each transaction when the bridge initiates transactions as a master, on the primary (P) and secondary (S) buses, and when the bridge responds to transactions as a target, on the primary (P) and secondary (S) buses. Table 2-1. PCI Transactions
Types of Transactions 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Initiates as Master Primary N Y Y Y N N Y Y N N N Y (Type 1 only) Y Secondary N Y Y Y N N Y Y N N Y Y Y Responds as Target Primary Secondary N N N N Y Y Y Y N N N N Y Y Y Y N N N N Y N Y Y (Type 1 only) Y Y
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Types of Transactions 1101 1110 1111 Dual Address Cycle Memory Read Line Memory Write and Invalidate Initiates as Master Primary Y Y Y Responds as Target Primary Secondary Y Y Y Y Y Y
Secondary Y Y Y
As indicated in Table 2-1, the following PCI commands are not supported by the bridge: ! ! ! The bridge never initiates a PCI transaction with a reserved command code and, as a target, the bridge ignores reserved command codes. The bridge does not generate interrupt acknowledge transactions. The bridge ignores interrupt acknowledge transactions as a target. The bridge does not respond to special cycle transactions. The bridge cannot guarantee delivery of a special cycle transaction to downstream buses because of the broadcast nature of the special cycle command and the inability to control the transaction as a target. To generate special cycle transactions on other PCI buses, either upstream or downstream, Type 1 configuration write must be used. The bridge neither generates Type 0 configuration transactions on the primary PCI bus nor responds to Type 0 configuration transactions on the secondary PCI buses.
!
2.2
SINGLE ADDRESS PHASE
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and the bus command is driven on P_CBE[3:0]. The bridge supports the linear increment address mode only, which is indicated when the lowest two address bits are equal to zero. If either of the lowest two address bits is nonzero, the bridge automatically disconnects the transaction after the first data transfer.
2.3
DEVICE SELECT (DEVSEL#) GENERATION
The bridge always performs positive address decoding (medium decode) when accepting transactions on either the primary or secondary buses. The bridge never does subtractive decode.
2.4
DATA PHASE
The address phase of a PCI transaction is followed by one or more data phases. A data phase is completed when IRDY# and either TRDY# or STOP# are asserted. A transfer of data occurs only when both IRDY# and TRDY# are asserted during the same PCI clock cycle. The last data phase of a transaction is indicated when FRAME# is de-asserted and both TRDY# and IRDY# are asserted, or when IRDY# and STOP# are asserted. See Section 2.8 for further discussion of transaction termination. Depending on the command type, the bridge can support multiple data phase PCI transactions. For detailed descriptions of how the bridge imposes disconnect boundaries, see Section 2.5.4 for write address boundaries and Section 2.6.4 read address boundaries.
2.5
WRITE TRANSACTIONS
Write transactions are treated as either posted write or delayed write transactions. Table 2-2 shows the method of forwarding used for each type of write operation. Page 20 of 90 JUNE 2004 - Revision 1.04
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Table 2-2. Write Transaction Forwarding
Type of Transaction Memory Write Memory Write and Invalidate Memory Write to VGA memory I/O Write Type 1 Configuration Write Type of Forwarding Posted (except VGA memory) Posted Delayed Delayed Delayed
2.5.1
MEMORY WRITE TRANSACTIONS
Posted write forwarding is used for "Memory Write" and "Memory Write and Invalidate" transactions. When the bridge determines that a memory write transaction is to be forwarded across the bridge, the bridge asserts DEVSEL# with medium timing and TRDY# in the next cycle, provided that enough buffer space is available in the posted memory write queue for the address and at least one DWORD of data. Under this condition, the bridge accepts write data without obtaining access to the target bus. The bridge can accept one DWORD of write data every PCI clock cycle. That is, no target wait state is inserted. The write data is stored in an internal posted write buffers and is subsequently delivered to the target. The bridge continues to accept write data until one of the following events occurs: ! ! ! The initiator terminates the transaction by de-asserting FRAME# and IRDY#. An internal write address boundary is reached, such as a cache line boundary or an aligned 4KB boundary, depending on the transaction type. The posted write data buffer fills up.
When one of the last two events occurs, the bridge returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. Once the posted write data moves to the head of the posted data queue, the bridge asserts its request on the target bus. This can occur while the bridge is still receiving data on the initiator bus. When the grant for the target bus is received and the target bus is detected in the idle condition, the bridge asserts FRAME# and drives the stored write address out on the target bus. On the following cycle, the bridge drives the first DWORD of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received. As long as write data exists in the queue, the bridge can drive one DWORD of write data each PCI clock cycle; that is, no master wait states are inserted. If write data is flowing through the bridge and the initiator stalls, the bridge will signal the last data phase for the current transaction at the target bus if the queue empties. The bridge will restart the follow-on transactions if the queue has new data. The bridge ends the transaction on the target bus when one of the following conditions is met: ! ! ! ! All posted write data has been delivered to the target. The target returns a target disconnect or target retry (the bridge starts another transaction to deliver the rest of the write data). The target returns a target abort (the bridge discards remaining write data). The master latency timer expires, and the bridge no longer has the target bus grant (the bridge starts another transaction to deliver remaining write data).
Section 2.8.3.2 provides detailed information about how the bridge responds to target termination during posted write transactions.
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2.5.2
MEMORY WRITE AND INVALIDATE
Posted write forwarding is used for Memory Write and Invalidate transactions. If offset 74h bits [8:7] = 11, the bridge disconnects Memory Write and Invalidate commands at aligned cache line boundaries. The cache line size value in the cache line size register gives the number of DWORD in a cache line. If offset 74h bits [8:7] = 00, the bridge converts Memory Write and Invalidate transactions to Memory Write transactions at the destination. If the value in the cache line size register does meet the memory write and invalidate conditions, the bridge returns a target disconnect to the initiator on a cache line boundary.
2.5.3
DELAYED WRITE TRANSACTIONS
Delayed write forwarding is used for I/O write transactions and Type 1 configuration write transactions. A delayed write transaction guarantees that the actual target response is returned back to the initiator without holding the initiating bus in wait states. A delayed write transaction is limited to a single DWORD data transfer. When a write transaction is first detected on the initiator bus, and the bridge forwards it as a delayed transaction, the bridge claims the access by asserting DEVSEL# and returns a target retry to the initiator. During the address phase, the bridge samples the bus command, address, and address parity one cycle later. After IRDY# is asserted, the bridge also samples the first data DWORD, byte enable bits, and data parity. This information is placed into the delayed transaction queue. The transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transaction queue is not full. When the delayed write transaction moves to the head of the delayed transaction queue and all ordering constraints with posted data are satisfied. The bridge initiates the transaction on the target bus. The bridge transfers the write data to the target. If the bridge receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered. If the bridge is unable to deliver write data after 224 (default) or 232 (maximum) attempts, the bridge will report a system error. The bridge also asserts P_SERR# if the primary SERR# enable bit is set in the command register. See Section 5.4 for information on the assertion of P_SERR#. When the initiator repeats the same write transaction (same command, address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the bridge claims the access by asserting DEVSEL# and returns TRDY# to the initiator, to indicate that the write data was transferred. If the initiator requests multiple DWORD, the bridge also asserts STOP# in conjunction with TRDY# to signal a target disconnect. Note that only those bytes of write data with valid byte enable bits are compared. If any of the byte enable bits are turned off (driven HIGH), the corresponding byte of write data is not compared. If the initiator repeats the write transaction before the data has been transferred to the target, the bridge returns a target retry to the initiator. The bridge continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, the bridge does not make a new entry into the delayed transaction queue. Section 2.8.3.1 provides detailed information about how the bridge responds to target termination during delayed write transactions.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION The bridge implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction completion queue. The initial value of this timer can be set to the retry counter register offset 88h. If the initiator does not repeat the delayed write transaction before the discard timer expires, the bridge discards the delayed write completion from the delayed transaction completion queue. The bridge also conditionally asserts P_SERR# (see Section 5.4).
2.5.4
WRITE TRANSACTION BOUNDARIES
The bridge imposes internal address boundaries when accepting write data. The aligned address boundaries are used to prevent the bridge from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. The bridge returns a target disconnect to the initiator when it reaches the aligned address boundaries under conditions shown in Table 2-3. Table 2-3. Write Transaction Disconnect Address Boundaries
Type of Transaction Delayed Write Posted Memory Write Posted Memory Write Posted Memory Write and Invalidate Posted Memory Write and Invalidate Condition All Memory write disconnect control bit = 0(1) Memory write disconnect control bit = 1(1) Cache line size 1, 2, 4, 8, 16 Cache line size = 1, 2, 4, 8, 16 Aligned Address Boundary Disconnects after one data transfer 4KB aligned address boundary Disconnects at cache line boundary 4KB aligned address boundary
Cache line boundary if posted memory write data FIFO does not have enough space for the cache line Note 1. Memory write disconnect control bit is bit 1 of the chip control register at offset 44h in the configuration space.
2.5.5
BUFFERING MULTIPLE WRITE TRANSACTIONS
The bridge continues to accept posted memory write transactions as long as space for at least one DWORD of data in the posted write data buffer remains. If the posted write data buffer fills before the initiator terminates the write transaction, the bridge returns a target disconnect to the initiator. Delayed write transactions are posted as long as at least one open entry in the delayed transaction queue exists. Therefore, several posted and delayed write transactions can exist in data buffers at the same time. See Chapter 5 for information about how multiple posted and delayed write transactions are ordered.
2.5.6
FAST BACK-TO-BACK TRANSACTIONS
The bridge can recognize and post fast back-to-back write transactions. When the bridge cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. The fast back-to-back enable bit must be set in the command register for upstream write transactions, and in the bridge control register for downstream write transactions.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
2.6
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing the bridge. Delayed read transactions are treated as either prefetchable or non-prefetchable. Table 2-5 shows the read behavior, prefetchable or non-prefetchable, for each type of read operation.
2.6.1
PREFETCHABLE READ TRANSACTIONS
A prefetchable read transaction is a read transaction where the bridge performs speculative DWORD reads, transferring data from the target before it is requested from the initiator. This behavior allows a prefetchable read transaction to consist of multiple data transfers. However, byte enable bits cannot be forwarded for all data phases as is done for the single data phase of the non-prefetchable read transaction. For prefetchable read transactions, the bridge forces all byte enable bits to be turned on for all data phases. Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memory space. The amount of data that is pre-fetched depends on the type of transaction. The amount of pre-fetching may also be affected by the amount of free buffer space available in the bridge, and by any read address boundaries encountered. Pre-fetching should not be used for those read transactions that have side effects in the target device, that is, control and status registers, FIFO's, and so on. The target device's base address register or registers indicate if a memory address region is prefetchable.
2.6.2
DYNAMIC PREFETCHING CONTROL
For prefetchable reads described in the previous section, the prefetching length is normally predefined and cannot be changed once it is set. This may cause some inefficiency as the prefetching length determined could be larger or smaller than the actual data being prefetched. To make prefetching more efficient, PI7C8148A incorporates dynamic prefetching control logic. This logic regulates the different PCI memory read commands (MR - memory read, MRL - memory read line, and MRM - memory read multiple) to improve memory read burst performance. The bridge tracks every memory read burst transaction and tallies the status. By using the status information, the bridge can determine to increase, reduce, or keep the same cache line length to be prefetched. Over time, the bridge can better match the correct cache line setting to the length of data being requested. The dynamic prefetching control logic is set with bits[3:2] offset 48h.
2.6.3
NON-PREFETCHABLE READ TRANSACTIONS
A non-prefetchable read transaction is a read transaction where the bridge requests one and only one DWORD from the target and disconnects the initiator after delivery of the first DWORD of read data. Unlike prefetchable read transactions, the bridge forwards the read byte enable information for the data phase. Non-prefetchable behavior is used for I/O and configuration read transactions, as well as for memory read transactions that fall into non-prefetchable memory space. Page 24 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
If extra read transactions could have side effects, for example, when accessing a FIFO, use nonprefetchable read transactions to those locations. Accordingly, if it is important to retain the value of the byte enable bits during the data phase, use non-prefetchable read transactions. If these locations are mapped in memory space, use the memory read command and map the target into non-prefetchable (memory-mapped I/O) memory space to use non-prefetching behavior.
2.6.4
READ PREFETCH ADDRESS BOUNDARIES
The bridge imposes internal read address boundaries on read pre-fetched data. When a read transaction reaches one of these aligned address boundaries, the bridge stops pre-fetched data, unless the target signals a target disconnect before the read pre-fetched boundary is reached. When the bridge finishes transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless the initiator completes the transaction before all pre-fetched read data is delivered. Any leftover prefetched data is discarded. Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address boundary, or until the initiator de-asserts FRAME_L. Section 2.6.7 describes flow-through mode during read operations. Table 2-4 shows the read prefetch address boundaries for read transactions during non-flow-through mode. Table 2-4. Read Prefetch Address Boundaries
Cache Line Size (CLS) Configuration Read * I/O Read * Memory Read Non-Prefetchable * Memory Read Prefetchable CLS = 0 or 16 Memory Read Prefetchable CLS = 1, 2, 4, 8, 16 Memory Read Line CLS = 0 or 16 Memory Read Line CLS = 1, 2, 4, 8, 16 Memory Read Multiple CLS = 0 or 16 Memory Read Multiple CLS = 1, 2, 4, 8, 16 - does not matter if it is prefetchable or non-prefetchable * don't care Type of Transaction Address Space Prefetch Aligned Address Boundary One DWORD (no prefetch) One DWORD (no prefetch) One DWORD (no prefetch) 16-DWORD aligned address boundary Cache line address boundary 16-DWORD aligned address boundary Cache line boundary 32-DWORD aligned address boundary 2X of cache line boundary
Table 2-5. Read Transaction Prefetching
Read Behavior Prefetching never allowed Prefetching never allowed Downstream: Prefetching used if address is prefetchable space Memory Read Upstream: Prefetching used or programmable Memory Read Line Prefetching always used Memory Read Multiple Prefetching always used See Section 3.3 for detailed information about prefetchable and non-prefetchable address spaces. Type of Transaction I/O Read Configuration Read
2.6.5
DELAYED READ REQUESTS
The bridge treats all read transactions as delayed read transactions, which means that the read request from the initiator is posted into a delayed transaction queue. Read data from the target is placed in the Page 25 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION read data queue directed toward the initiator bus interface and is transferred to the initiator when the initiator repeats the read transaction. When the bridge accepts a delayed read request, it first samples the read address, read bus command, and address parity. When IRDY# is asserted, the bridge then samples the byte enable bits for the first data phase. This information is entered into the delayed transaction queue. The bridge terminates the transaction by signaling a target retry to the initiator. Upon reception of the target retry, the initiator is required to continue to repeat the same read transaction until at least one data transfer is completed, or until a target response (target abort or master abort) other than a target retry is received.
2.6.6
DELAYED READ COMPLETION WITH TARGET
When delayed read request reaches the head of the delayed transaction queue, the bridge arbitrates for the target bus and initiates the read transaction only if all previously queued posted write transactions have been delivered. The bridge uses the exact read address and read command captured from the initiator during the initial delayed read request to initiate the read transaction. If the read transaction is a non-prefetchable read, the bridge drives the captured byte enable bits during the next cycle. If the transaction is a prefetchable read transaction, it drives all byte enable bits to zero for all data phases. If the bridge receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered. If the transaction is terminated via normal master termination or target disconnect after at least one data transfer has been completed, the bridge does not initiate any further attempts to read more data. If the bridge is unable to obtain read data from the target after 224 (default) or 232 (maximum) attempts, the bridge will report system error. The number of attempts is programmable. The bridge also asserts P_SERR# if the primary SERR# enable bit is set in the command register. See Section 5.4 for information on the assertion of P_SERR#. Once the bridge receives DEVSEL# and TRDY# from the target, it transfers the data read to the opposite direction read data queue, pointing toward the opposite inter-face, before terminating the transaction. For example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read data queue. The bridge can accept one DWORD of read data each PCI clock cycle; that is, no master wait states are inserted. The number of DWORD's transferred during a delayed read transaction depends on the conditions given in Table 2-4 (assuming no disconnect is received from the target).
2.6.7
DELAYED READ COMPLETION ON INITIATOR BUS
When the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the bridge transfers the data to the initiator when the initiator repeats the transaction. For memory read transactions, the bridge aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. The bridge returns a target disconnect along with the transfer of the last DWORD of read data to the initiator. If the bridge initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded. When the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. Because data is flowing Page 26 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION through the data buffers from the target to the initiator, long read bursts can then be sustained. In this case, the read transaction is allowed to continue until the initiator terminates the transaction, or until an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes first. When the buffer empties, the bridge reflects the stalled condition to the initiator by disconnecting the initiator with data. The initiator may retry the transaction later if data are needed. If the initiator does not need any more data, the initiator will not continue the disconnected transaction. In this case, the bridge will start the master timeout timer. The remaining read data will be discarded after the master timeout timer expires. To provide better latency, if there are any other pending data for other transactions in the RDB (Read Data Buffer), the remaining read data will be discarded even though the master timeout timer has not expired. The bridge implements a master timeout timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. The initial value of this timer is programmable through configuration register. If the initiator does not repeat the read transaction and before the master timeout timer expires (215 default), the bridge discards the read transaction and read data from its queues. The bridge also conditionally asserts P_SERR# (see Section 5.4). The bridge has the capability to post multiple delayed read requests, up to a maximum of four in each direction. If an initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted as it is already contained in the delayed transaction queue. See Section 4 for a discussion of how delayed read transactions are ordered when crossing the bridge.
2.6.8
FAST BACK-TO-BACK READ TRANSACTIONS
The bridge can recognize fast back-to-back read transactions.
2.7
CONFIGURATION TRANSACTIONS
Configuration transactions are used to initialize a PCI system. Every PCI device has a configuration space that is accessed by configuration commands. All registers are accessible in configuration space only. In addition to accepting configuration transactions for initialization of its own configuration space, the bridge also forwards configuration transactions for device initialization in hierarchical PCI systems, as well as for special cycle generation. To support hierarchical PCI bus systems, two types of configuration transactions are specified: Type 0 and Type 1. Type 0 configuration transactions are issued when the intended target resides on the same PCI bus as the initiator. A Type 0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b. Type 1 configuration transactions are issued when the intended target resides on another PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed. For single-function devices, this value is not decoded. The addresses of Type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target PCI bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI bus to which the transaction is targeted.
2.7.1
TYPE 0 ACCESS TO PI7C8148A
The configuration space is accessed by a Type 0 configuration transaction on the primary interface. The configuration space cannot be accessed from the secondary bus. The bridge responds to a Type 0 configuration transaction by asserting P_DEVSEL# when the following conditions are met during the address phase: ! ! ! The bus command is a configuration read or configuration write transaction. Lowest two address bits P_AD[1:0] must be 00b. Signal P_IDSEL must be asserted.
The bridge limits all configuration access to a single DWORD data transfer and returns targetdisconnect with the first data transfer if additional data phases are requested. Because read transactions to configuration space do not have side effects, all bytes in the requested DWORD are returned, regardless of the value of the byte enable bits. Type 0 configuration write and read transactions do not use data buffers; that is, these transactions are completed immediately, regardless of the state of the data buffers. The bridge ignores all Type 0 transactions initiated on the secondary interface.
2.7.2
TYPE 1 TO TYPE 0 CONVERSION
Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI bus system. A PCI-to-PCI bridge is the only type of device that should respond to a Type 1 configuration command. Type 1 configuration commands are used when the configuration access is intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. The bridge performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. The bridge must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction; that is, the bridge generates a Type 0 transaction only on the secondary bus, and never on the primary bus. The bridge responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met during the address phase: ! ! ! The lowest two address bits on P_AD[1:0] are 01b. The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in configuration space. The bus command on P_CBE[3:0] is a configuration read or configuration write transaction. When the bridge translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it performs the following translations to the address: Page 28 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! ! ! ! Sets the lowest two address bits on S_AD[1:0]. Decodes the device number and drives the bit pattern specified in Table 2-6 on S_AD[31:16] for the purpose of asserting the device's IDSEL signal. Sets S_AD[15:11] to 0. Leaves unchanged the function number and register number fields.
The bridge asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on the device number in the Type 1 address bits P_AD[15:11]. presents the mapping that the bridge uses. Table 2-6. Device Number to IDSEL S_AD Pin Mapping
Device Number 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h - 1Eh 1Fh P_AD[15:11] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 - 11110 11111 Secondary IDSEL S_AD[31:16] 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 Generate special cycle (P_AD[7:2] > 00h) 0000 0000 0000 0000 (P_AD[7:2] = 00h) S_AD 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 -
The bridge can assert up to 16 unique address lines to be used as IDSEL signals for up to 16 devices on the secondary bus, for device numbers ranging from 0 through 15. Because of electrical loading constraints of the PCI bus, more than 9 IDSEL signals should not be necessary. However, if device numbers greater than 15 are desired, some external method of generating IDSEL lines must be used, and no upper address bits are then asserted. The configuration transaction is still translated and passed from the primary bus to the secondary bus. If no IDSEL pin is asserted to a secondary device, the transaction ends in a master abort. The bridge forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions. Type 1 to Type 0 configuration read or write transactions are limited to a single 32-bit data transfer.
2.7.3
TYPE 1 TO TYPE 1 FORWARDING
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of PCI-to-PCI bridges are used. When the bridge detects a Type 1 configuration transaction intended for a PCI bus downstream from the secondary bus, the bridge forwards the transaction unchanged to the secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1 to Type 1 forwarding occurs when the following conditions are met during the address phase: ! The lowest two address bits are equal to 01b. Page 29 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! ! The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. The bus command is a configuration read or write transaction.
The bridge also supports Type 1 to Type 1 forwarding of configuration write transactions upstream to support upstream special cycle generation. A Type 1 configuration command is forwarded upstream when the following conditions are met: ! ! ! ! ! The lowest two address bits are equal to 01b. The bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. The device number in address bits AD[15:11] is equal to 11111b. The function number in address bits AD[10:8] is equal to 111b. The bus command is a configuration write transaction.
The bridge forwards Type 1 to Type 1 configuration write transactions as delayed transactions. Type 1 to Type 1 configuration write transactions are limited to a single data transfer.
2.7.4
SPECIAL CYCLES
The Type 1 configuration mechanism is used to generate special cycle transactions in hierarchical PCI systems. Special cycle transactions are ignored by acting as a target and are not forwarded across the bridge. Special cycle transactions can be generated from Type 1 configuration write transactions in either the upstream or the down-stream direction. The birdge initiates a special cycle on the target bus when a Type 1 configuration write transaction is being detected on the initiating bus and the following conditions are met during the address phase: ! ! ! ! ! ! The lowest two address bits on AD[1:0] are equal to 01b. The device number in address bits AD[15:11] is equal to 11111b. The function number in address bits AD[10:8] is equal to 111b. The register number in address bits AD[7:2] is equal to 000000b. The bus number is equal to the value in the secondary bus number register in configuration space for downstream forwarding or equal to the value in the primary bus number register in configuration space for upstream forwarding. The bus command on CBE# is a configuration write command.
When the bridge initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. The address and data are for-warded unchanged. Devices that use special cycles ignore the address and decode only the bus command. The data phase contains the special cycle message. The transaction is forwarded as a delayed transaction, but in this case the target response is not forwarded back (because special cycles result in a master abort). Once the transaction is completed on the target bus, through detection of the master abort condition, the bridge responds with TRDY# to the next attempt of the con-figuration transaction from the initiator. If more than one data transfer is requested, the bridge responds with a target disconnect operation during the first data phase.
2.8
TRANSACTION TERMINATION
This section describes how bridge returns transaction termination conditions back to the initiator. The initiator can terminate transactions with one of the following types of termination: Page 30 of 90 JUNE 2004 - Revision 1.04
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!
!
Normal termination Normal termination occurs when the initiator de-asserts FRAME# at the beginning of the last data phase, and de-asserts IRDY# at the end of the last data phase in conjunction with either TRDY# or STOP# assertion from the target. Master abort A master abort occurs when no target response is detected. When the initiator does not detect a DEVSEL# from the target within five clock cycles after asserting FRAME#, the initiator terminates the transaction with a master abort. If FRAME# is still asserted, the initiator de-asserts FRAME# on the next cycle, and then de-asserts IRDY# on the following cycle. IRDY# must be asserted in the same cycle in which FRAME# de-asserts. If FRAME# is already de-asserted, IRDY# can be de-asserted on the next clock cycle following detection of the master abort condition.
The target can terminate transactions with one of the following types of termination: ! ! ! ! ! Normal termination TRDY# and DEVSEL# asserted in conjunction with FRAME# de-asserted and IRDY# asserted. Target retry STOP# and DEVSEL# asserted with TRDY# de-asserted during the first data phase. No data transfers occur during the transaction. This transaction must be repeated. Target disconnect with data transfer STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the transaction. Target disconnect without data transfer STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been made. Indicates that no more data transfers will be made during this transaction. Target abort STOP# asserted with DEVSEL# and TRDY# de-asserted. Indicates that target will never be able to complete this transaction. DEVSEL# must be asserted for at least one cycle during the transaction before the target abort is signaled.
2.8.1
MASTER TERMINATION INITIATED BY PI7C8148A
The bridge, as an initiator, uses normal termination if DEVSEL# is returned by target within five clock cycles of the bridge's assertion of FRAME# on the target bus. As an initiator, the bridge terminates a transaction when the following conditions are met: ! ! ! ! ! ! During a delayed write transaction, a single DWORD is delivered. During a non-prefetchable read transaction, a single DWORD is transferred from the target. During a prefetchable read transaction, a pre-fetch boundary is reached. For a posted write transaction, all write data for the transaction is transferred from data buffers to the target. For burst transfer, with the exception of "Memory Write and Invalidate" transactions, the master latency timer expires and the bridge's bus grant is de-asserted. The target terminates the transaction with a retry, disconnect, or target abort.
If the bridge is delivering posted write data when it terminates the transaction because the master latency timer expires, it initiates another transaction to deliver the remaining write data. The address of the transaction is updated to reflect the address of the current DWORD to be delivered. If the bridge is pre-fetching read data when it terminates the transaction because the master latency timer expires, it does not repeat the transaction to obtain more data. Page 31 of 90 JUNE 2004 - Revision 1.04
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2.8.2
MASTER ABORT RECEIVED BY PI7C8148A
If the initiator initiates a transaction on the target bus and does not detect DEVSEL# returned by the target within five clock cycles of the assertion of FRAME#, the bridge terminates the transaction with a master abort. This sets the received-master-abort bit in the status register corresponding to the target bus. For delayed read and write transactions, the bridge is able to reflect the master abort condition back to the initiator. When the bridge detects a master abort in response to a delayed transaction, and when the initiator repeats the transaction, the bridge does not respond to the transaction with DEVSEL#, which induces the master abort condition back to the initiator. The transaction is then removed from the delayed transaction queue. When a master abort is received in response to a posted write transaction, the bridge discards the posted write data and makes no more attempts to deliver the data. The bridge sets the received-master-abort bit in the status register when the master abort is received on the primary bus, or it sets the received master abort bit in the secondary status register when the master abort is received on the secondary interface. When master abort is detected in posted write transaction with both master-abort-mode bit (bit 5 of bridge control register) and the SERR# enable bit (bit 8 of command register for secondary bus) are set, the bridge asserts P_SERR# if the master-abort-on-posted-write is not set. The master-abort-on-posted-write bit is bit 4 of the P_SERR# event disable register (offset 64h). Note: When the bridge performs a Type 1 to special cycle conversion, a master abort is the expected termination for the special cycle on the target bus. In this case, the master abort received bit is not set, and the Type 1 configuration transaction is disconnected after the first data phase.
2.8.3
TARGET TERMINATION RECEIVED BY PI7C8148A
When the bridge initiates a transaction on the target bus and the target responds with DEVSEL#, the target can end the transaction with one of the following types of termination: ! ! ! ! Normal termination (upon de-assertion of FRAME#) Target retry Target disconnect Target abort
The bridge handles these terminations in different ways, depending on the type of transaction being performed. 2.8.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE When the bridge initiates a delayed write transaction, the type of target termination received from the target can be passed back to the initiator. Table 2-7 shows the response to each type of target termination that occurs during a delayed write transaction. The bridge repeats a delayed write transaction until one of the following conditions is met: ! ! ! Bridge completes at least one data transfer. Bridge receives a master abort. Bridge receives a target abort.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION The bridge makes 224 (default) or 232 (maximum) write attempts resulting in a response of target retry. Table 2-7. Delayed Write Target Termination Response
Target Termination Normal Target Retry Target Disconnect Target Abort Response Returning disconnect to initiator with first data transfer only if multiple data phases requested. Returning target retry to initiator. Continue write attempts to target Returning disconnect to initiator with first data transfer only if multiple data phases requested. Returning target abort to initiator. Set received target abort bit in target interface status register. Set signaled target abort bit in initiator interface status register.
After the bridge makes 224 (default) attempts of the same delayed write trans-action on the target bus, the bridge asserts P_SERR# if the SERR# enable bit (bit 8 of command register for the secondary bus) is set and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register (offset 64h). The bridge will report system error. See Section 5.4 for a description of system error conditions. 2.8.3.2 POSTED WRITE TARGET TERMINATION RESPONSE When the bridge initiates a posted write transaction, the target termination cannot be passed back to the initiator. Table 2-8 shows the response to each type of target termination that occurs during a posted write transaction. Table 2-8. Response to Posted Write Target Termination
Target Termination Normal Target Retry Target Disconnect Target Abort Repsonse No additional action. Repeating write transaction to target. Initiate write transaction for delivering remaining posted write data. Set received-target-abort bit in the target interface status register. Assert P_SERR# if enabled, and set the signaled-system-error bit in primary status register.
Note that when a target retry or target disconnect is returned and posted write data associated with that transaction remains in the write buffers, the bridge initiates another write transaction to attempt to deliver the rest of the write data. If there is a target retry, the exact same address will be driven as for the initial write trans-action attempt. If a target disconnect is received, the address that is driven on a subsequent write transaction attempt will be updated to reflect the address of the current DWORD. If the initial write transaction is Memory-Write-and-Invalidate transaction, and a partial delivery of write data to the target is performed before a target disconnect is received, the bridge will use the memory write command to deliver the rest of the write data. It is because an incomplete cache line will be transferred in the subsequent write transaction attempt. After the bridge makes 224 (default) write transaction attempts and fails to deliver all posted write data associated with that transaction, the bridge asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for secondary bus) and posted-write-non-delivery bit is not set. The postedwrite-non-delivery bit is the bit 2 of P_SERR# event disable register (offset 64h). The bridge will report system error. See Section 5.4 for a discussion of system error conditions.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
2.8.3.3 DELAYED READ TARGET TERMINATION RESPONSE When the bridge initiates a delayed read transaction, the abnormal target responses can be passed back to the initiator. Other target responses depend on how much data the initiator requests. Table 2-9 shows the response to each type of target termination that occurs during a delayed read transaction. The bridge repeats a delayed read transaction until one of the following conditions is met: ! ! ! Bridge completes at least one data transfer. Bridge receives a master abort. Bridge receives a target abort.
The bridge makes 224 (default) read attempts resulting in a response of target retry. Table 2-9. Response to Delayed Read Target Termination
Target Termination Normal Target Retry Target Disconnect Target Abort Response If prefetchable, target disconnect only if initiator requests more data than read from target. If non-prefetchable, target disconnect on first data phase. Re-initiate read transaction to target If initiator requests more data than read from target, return target disconnect to initiator. Return target abort to initiator. Set received target abort bit in the target interface status register. Set signaled target abort bit in the initiator interface status register.
After the bridge makes 224(default) attempts of the same delayed read transaction on the target bus, the bridge asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for secondary bus) and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register (offset 64h). The bridge will report system error. See Section 5.4 for a description of system error conditions.
2.8.4
TARGET TERMINATION INITIATED BY PI7C8148A
The bridge can return a target retry, target disconnect, or target abort to an initiator for reasons other than detection of that condition at the target interface.
2.8.4.1 TARGET RETRY The bridge returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. The bridge returns a target retry to an initiator when any of the following conditions is met: For delayed write transactions: ! ! ! ! ! ! ! The transaction is being entered into the delayed transaction queue. Transaction has already been entered into delayed transaction queue, but target response has not yet been received. Target response has been received but has not progressed to the head of the return queue. The delayed transaction queue is full, and the transaction cannot be queued. A transaction with the same address and command has been queued. A locked sequence is being propagated across the bridge, and the write transaction is not a locked transaction. The target bus is locked and the write transaction is a locked transaction. Page 34 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! Use more than 16 clocks to accept this transaction.
For delayed read transactions: ! ! ! ! ! ! ! ! ! The transaction is being entered into the delayed transaction queue. The read request has already been queued, but read data is not yet available. Data has been read from target, but it is not yet at head of the read data queue or a posted write transaction precedes it. The delayed transaction queue is full, and the transaction cannot be queued. A delayed read request with the same address and bus command has already been queued. A locked sequence is being propagated across the bridge, and the read transaction is not a locked transaction. The bridge is currently discarding previously pre-fetched read data. The target bus is locked and the write transaction is a locked transaction. Use more than 16 clocks to accept this transaction.
For posted write transactions: ! ! ! The posted write data buffer does not have enough space for address and at least one DWORD of write data. A locked sequence is being propagated across the bridge, and the write transaction is not a locked transaction. When a target retry is returned to the initiator of a delayed transaction, the initiator must repeat the transaction with the same address and bus command as well as the data if it is a write transaction, within the time frame specified by the master timeout value. Otherwise, the transaction is discarded from the buffers.
2.8.4.2 TARGET DISCONNECT The bridge returns a target disconnect to an initiator when one of the following conditions is met: ! ! ! Bridge hits an internal address boundary. Bridge cannot accept any more write data. Bridge has no more read data to deliver.
See Section 2.5.4 for a description of write address boundaries, and Section 2.6.4 for a description of read address boundaries. 2.8.4.3 TARGET ABORT The bridge returns a target abort to an initiator when one of the following conditions is met: ! ! The bridge is returning a target abort from the intended target. When the bridge returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface.
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3
ADDRESS DECODING
The bridge uses three address ranges that control I/O and memory transaction forwarding. These address ranges are defined by base and limit address registers in the configuration space. This chapter describes these address ranges, as well as ISA-mode and VGA-addressing support.
3.1
ADDRESS RANGES
The bridge uses the following address ranges that determine which I/O and memory transactions are forwarded from the primary PCI bus to the secondary PCI bus, and from the secondary bus to the primary bus: ! ! ! Two 32-bit I/O address ranges Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges Two 32-bit prefetchable memory address ranges
Transactions falling within these ranges are forwarded downstream from the primary PCI bus to the secondary PCI bus. Transactions falling outside these ranges are forwarded upstream from the secondary PCI bus to the primary PCI bus. No address translation is required in the bridge. The addresses that are not marked for downstream are always forwarded upstream.
3.2
I/O ADDRESS DECODING
The bridge uses the following mechanisms that are defined in the configuration space to specify the I/O address space for downstream and upstream forwarding: ! ! ! ! I/O base and limit address registers The ISA enable bit The VGA mode bit The VGA snoop bit
This section provides information on the I/O address registers and ISA mode. Section 3.4 provides information on the VGA modes. To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the command register in configuration space. All I/O transactions initiated on the primary bus will be ignored if the I/O enable bit is not set. To enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the master-enable bit is not set, the bridge ignores all I/O and memory transactions initiated on the secondary bus. The master-enable bit also allows upstream forwarding of memory transactions if it is set. CAUTION If any configuration state affecting I/O transaction forwarding is changed by a configuration write operation on the primary bus at the same time that I/O transactions are ongoing on the secondary bus, the bridge response to the secondary bus I/O transactions is not predictable. Configure the I/O base and limit address registers, ISA enable bit, VGA mode bit, and VGA snoop bit before setting I/O enable Page 36 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle.
3.2.1
I/O BASE AND LIMIT ADDRESS REGISTER
The bridge implements one set of I/O base and limit address registers in configuration space that define an I/O address range per port downstream forwarding. The bridge supports 32-bit I/O addressing, which allows I/O addresses downstream of the bridge to be mapped anywhere in a 4GB I/O address space. I/O transactions with addresses that fall inside the range defined by the I/O base and limit registers are forwarded downstream from the primary PCI bus to the secondary PCI bus. I/O transactions with addresses that fall outside this range are forwarded upstream from the secondary PCI bus to the primary PCI bus. The I/O range can be turned off by setting the I/O base address to a value greater than that of the I/O limit address. When the I/O range is turned off, all I/O trans-actions are forwarded upstream, and no I/O transactions are forwarded downstream. The I/O range has a minimum granularity of 4KB and is aligned on a 4KB boundary. The maximum I/O range is 4GB in size. The I/O base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at address 30h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O base address. The bottom 4 bits read only as 1h to indicate that the bridge supports 32-bit I/O addressing. Bits [11:0] of the base address are assumed to be 0, which naturally aligns the base address to a 4KB boundary. The 16 bits contained in the I/O base upper 16 bits register at configuration offset 30h define AD[31:16] of the I/O base address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O base address is initialized to 0000 0000h. The I/O limit register consists of an 8-bit field at configuration offset 1Dh and a 16-bit field at offset 32h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O limit address. The bottom 4 bits read only as 1h to indicate that 32-bit I/O addressing is supported. Bits [11:0] of the limit address are assumed to be FFFh, which naturally aligns the limit address to the top of a 4KB I/O address block. The 16 bits contained in the I/O limit upper 16 bits register at configuration offset 32h define AD[31:16] of the I/O limit address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O limit address is reset to 0000 0FFFh. Note: The initial states of the I/O base and I/O limit address registers define an I/O range of 0000 0000h to 0000 0FFFh, which is the bottom 4KB of I/O space. Write these registers with their appropriate values before setting either the I/O enable bit or the master enable bit in the command register in configuration space.
3.2.2
ISA MODE
The bridge supports ISA mode by providing an ISA enable bit in the bridge control register in configuration space. ISA mode modifies the response of the bridge inside the I/O address range in order to support mapping of I/O space in the presence of an ISA bus in the system. This bit only affects the response of the bridge when the transaction falls inside the address range defined by the I/O base and limit address registers, and only when this address also falls inside the first 64KB of I/O space (address bits [31:16] are 0000h). When the ISA enable bit is set, the bridge does not forward downstream any I/O transactions addressing the top 768 bytes of each aligned 1KB block. Only those transactions addressing the bottom 256 bytes of an aligned 1KB block inside the base and limit I/O address range are forwarded downstream. Transactions above the 64KB I/O address boundary are forwarded as defined by the address range defined by the I/O base and limit registers.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Accordingly, if the ISA enable bit is set, the bridge forwards upstream those I/O transactions addressing the top 768 bytes of each aligned 1KB block within the first 64KB of I/O space. The master enable bit in the command configuration register must also be set to enable upstream forwarding. All other I/O transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I/O address range. When the ISA enable bit is set, devices downstream of the bridge can have I/O space mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary.
3.3
MEMORY ADDRESS DECODING
The bridge has three mechanisms for defining memory address ranges for forwarding of memory transactions: ! ! ! Memory-mapped I/O base and limit address registers Prefetchable memory base and limit address registers VGA mode
This section describes the first two mechanisms. Section 3.4.1 describes VGA mode. To enable downstream forwarding of memory transactions, the memory enable bit must be set in the command register in configuration space. To enable upstream forwarding of memory transactions, the masterenable bit must be set in the command register. The master-enable bit also allows upstream forwarding of I/O transactions if it is set. CAUTION If any configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus at the same time that memory transactions are ongoing on the secondary bus, response to the secondary bus memory transactions is not predictable. Configure the memorymapped I/O base and limit address registers, prefetchable memory base and limit address registers, and VGA mode bit before setting the memory enable and master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle.
3.3.1
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS
Memory-mapped I/O is also referred to as non-prefetchable memory. Memory addresses that cannot automatically be pre-fetched but that can be conditionally pre-fetched based on command type should be mapped into this space. Read transactions to non-prefetchable space may exhibit side effects; this space may have non-memory-like behavior. The bridge prefetches in this space only if the memory read line or memory read multiple commands are used; transactions using the memory read command are limited to a single data transfer. The memory-mapped I/O base address and memory-mapped I/O limit address registers define an address range that the bridge uses to determine when to forward memory commands. The bridge forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the memory-mapped I/O address range. The bridge ignores memory transactions initiated on the secondary interface that fall into this address range. Any transactions that fall outside this address range are ignored on the primary interface and are forwarded upstream from the secondary interface (provided that they do not fall into the prefetchable memory range or are not forwarded downstream by the VGA mechanism).
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION The memory-mapped I/O range supports 32-bit addressing only. The PCI-to-PCI Bridge Architecture Specification does not provide for 64-bit addressing in the memory-mapped I/O space. The memorymapped I/O address range has a granularity and alignment of 1MB. The maximum memory-mapped I/O address range is 4GB. The memory-mapped I/O address range is defined by a 16-bit memory-mapped I/O base address register at configuration offset 20h and by a 16-bit memory-mapped I/O limit address register at offset 22h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The low 4 bits are hardwired to 0. The lowest 20 bits of the memory-mapped I/O base address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary. The lowest 20 bits of the memory-mapped I/O limit address are assumed to be FFFFFh, which results in an alignment to the top of a 1MB block. Note: The initial state of the memory-mapped I/O base address register is 0000 0000h. The initial state of the memory-mapped I/O limit address register is 000F FFFFh. Note that the initial states of these registers define a memory-mapped I/O range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. To turn off the memory-mapped I/O address range, write the memory-mapped I/O base address register with a value greater than that of the memory-mapped I/O limit address register.
3.3.2
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS
Locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable memory location must have no side effects. The bridge prefetches for all types of memory read commands in this address space. The prefetchable memory base address and prefetchable memory limit address registers define an address range that the bridge uses to determine when to forward memory commands. The bridge forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the prefetchable memory address range. The bridge ignores memory transactions initiated on the secondary interface that fall into this address range. The bridge does not respond to any transactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that they do not fall into the memory-mapped I/O range or are not forwarded by the VGA mechanism). The prefetchable memory range supports 64-bit addressing and provides additional registers to define the upper 32 bits of the memory address range, the prefetchable memory base address upper 32 bits register, and the prefetchable memory limit address upper 32 bits register. For address comparison, a single address cycle (32-bit address) prefetchable memory transaction is treated like a 64-bit address transaction where the upper 32 bits of the address are equal to 0. This upper 32-bit value of 0 is compared to the prefetchable memory base address upper 32 bits register and the prefetchable memory limit address upper 32 bits register. The prefetchable memory base address upper 32 bits register must be 0 to pass any single address cycle transactions downstream. Prefetchable memory address range has a granularity and alignment of 1MB. Maximum memory address range is 4GB when 32-bit addressing is being used. Prefetchable memory address range is defined by a 16-bit prefetchable memory base address register at configuration offset 24h and by a 16bit prefetchable memory limit address register at offset 26h. The top 12 bits of each of these registers correspond to bits [31:20] of the memory address. The lowest 4 bits are hardwired to 1h. The lowest 20 bits of the prefetchable memory base address are assumed to be 0 0000h, which results in a natural Page 39 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION alignment to a 1MB boundary. The lowest 20 bits of the prefetchable memory limit address are assumed to be FFFFFh, which results in an alignment to the top of a 1MB block. Note: The initial state of the prefetchable memory base address register is 0000 0000h. The initial state of the prefetchable memory limit address register is 000F FFFFh. Note that the initial states of these registers define a prefetchable memory range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. To turn off the prefetchable memory address range, write the prefetchable memory base address register with a value greater than that of the prefetchable memory limit address register. The entire base value must be greater than the entire limit value, meaning that the upper 32 bits must be considered. Therefore, to disable the address range, the upper 32 bits registers can both be set to the same value, while the lower base register is set greater than the lower limit register. Otherwise, the upper 32-bit base must be greater than the upper 32-bit limit.
3.4 VGA SUPPORT
The bridge provides two modes for VGA support: ! ! VGA mode, supporting VGA-compatible addressing VGA snoop mode, supporting VGA palette forwarding
3.4.1
VGA MODE
When a VGA-compatible device exists downstream from the bridge, set the VGA mode bit in the bridge control register in configuration space to enable VGA mode. When the bridge is operating in VGA mode, it forwards downstream those transactions addressing the VGA frame buffer memory and VGA I/O registers, regardless of the values of the base and limit address registers. The bridge ignores transactions initiated on the secondary interface addressing these locations. The VGA frame buffer consists of the following memory address range: 000A 0000h-000B FFFFh Read transactions to frame buffer memory are treated as non-prefetchable. The bridge requests only a single data transfer from the target, and read byte enable bits are forwarded to the target bus. The VGA I/O addresses are in the range of 3B0h-3BBh and 3C0h-3DFh I/O. These I/O addresses are aliases every 1KB throughout the first 64KB of I/O space. This means that address bits <15:10> are not decoded and can be any value, while address bits [31:16] must be all 0's. VGA BIOS addresses starting at C0000h are not decoded in VGA mode.
3.4.2
VGA SNOOP MODE
The bridge provides VGA snoop mode, allowing for VGA palette write transactions to be forwarded downstream. This mode is used when a graphics device downstream from the bridge needs to snoop or respond to VGA palette write transactions. To enable the mode, set the VGA snoop bit in the command
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION register in configuration space. Note that the bridge claims VGA palette write transactions by asserting DEVSEL# in VGA snoop mode. When VGA snoop bit is set, the bridge forwards downstream transactions within the 3C6h, 3C8h and 3C9h I/O addresses space. Note that these addresses are also forwarded as part of the VGA compatibility mode previously described. Again, address bits <15:10> are not decoded, while address bits <31:16> must be equal to 0, which means that these addresses are aliases every 1KB throughout the first 64KB of I/O space. Note: If both the VGA mode bit and the VGA snoop bit are set, the bridge behaves in the same way as if only the VGA mode bit were set.
4
TRANSACTION ORDERING
To maintain data coherency and consistency, the bridge complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.2, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction forwarding across the bridge.
4.1
TRANSACTIONS GOVERNED BY ORDERING RULES
Ordering relationships are established for the following classes of transactions crossing the bridge: Posted write transactions, comprised of memory write and memory write and invalidate transactions. Posted write transactions complete at the source before they complete at the destination; that is, data is written into intermediate data buffers before it reaches the target. Delayed write request transactions, comprised of I/O write and configuration write transactions. Delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. A delayed write transaction must complete on the target bus before it completes on the initiator bus. Delayed write completion transactions, comprised of I/O write and configuration write transactions. Delayed write completion transactions complete on the target bus, and the target response is queued in the buffers. A delayed write completion transaction proceeds in the direction opposite that of the original delayed write request; that is, a delayed write completion transaction proceeds from the target bus to the initiator bus. Delayed read request transactions, comprised of all memory read, I/O read, and configuration read transactions. Delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. Delayed read completion transactions, comprised of all memory read, I/O read, & configuration read transactions. Delayed read completion transactions complete on the target bus, and the read data is queued in the read data buffers. A delayed read completion transaction proceeds in the direction opposite that of the original delayed read request; that is, a delayed read completion transaction proceeds from the target bus to the initiator bus. Page 41 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
The bridge does not combine or merge write transactions: ! ! ! The bridge does not combine separate write transactions into a single write transaction--this optimization is best implemented in the originating master. The bridge does not merge bytes on separate masked write transactions to the same DWORD address--this optimization is also best implemented in the originating master. The bridge does not collapse sequential write transactions to the same address into a single write transaction--the PCI Local Bus Specification does not permit this combining of transactions.
4.2
GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when those transactions cross the bridge. The following general ordering guidelines govern transactions crossing the bridge: ! ! The ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry. Requests terminated with target retry can be accepted and completed in any order with respect to other transactions that have been terminated with target retry. If the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one has been completed. If more than one delayed transaction is initiated, the initiator should repeat all delayed transaction requests, using some fairness algorithm. Repeating a delayed transaction cannot be contingent on completion of another delayed transaction. Otherwise, a deadlock can occur. Write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. The bridge can accept posted write transactions on both interfaces at the same time, as well as initiate posted write transactions on both interfaces at the same time. The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. This is true for the bridge and must also be true for other bus agents. Otherwise, a deadlock can occur. The bridge accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across the bridge.
!
!
!
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
4.3
ORDERING RULES
Table 4-1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow. Table 4-1. Summary of Transaction Ordering
Pass Posted Write Delayed Read Request Delayed Write Request Delayed Read Completion Delayed Write Completion Posted Write No1 No2 No4 No3 Yes Delayed Read Request Yes5 Yes Yes Yes Yes Delayed Write Request Yes5 Yes Yes Yes Yes Delayed Read Completion Yes5 Yes Yes Yes Yes Delayed Write Completion Yes5 Yes Yes Yes Yes
Note: The superscript accompanying some of the table entries refers to any applicable ordering rule listed in this section. Many entries are not governed by these ordering rules; therefore, the implementation can choose whether or not the transactions pass each other. The entries without superscripts reflect the bridge's implementation choices. The following ordering rules describe the transaction relationships. Each ordering rule is followed by an explanation, and the ordering rules are referred to by number in Table 4-1. These ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing the bridge in the same direction. Note that delayed completion transactions cross the bridge in the direction opposite that of the corresponding delayed requests. 1. Posted write transactions must complete on the target bus in the order in which they were received on the initiator bus. The subsequent posted write transaction can be setting a flag that covers the data in the first posted write transaction; if the second transaction were to complete before the first transaction, a device checking the flag could subsequently consume stale data. 2. A delayed read request traveling in the same direction as a previously queued posted write transaction must push the posted write data ahead of it. The posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. The read transaction can be to the same location as the write data, so if the read transaction were to pass the write transaction, it would return stale data. 3. A delayed read completion must ``pull'' ahead of previously queued posted write data traveling in the same direction. In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of the bridge as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator. The read transaction can be a reading to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete. 4. Delayed write requests cannot pass previously queued posted write data. For posted memory write transactions, the delayed write transaction can set a flag that covers the data in the posted write transaction. If the delayed write request were to complete before the earlier posted write transaction, a device checking the flag could subsequently consume stale data. 5. Posted write transactions must be given opportunities to pass delayed read and write requests and completions. Otherwise, deadlocks may occur when some bridges which support delayed transactions and other bridges which do not support delayed transactions are being used in the same system. A
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION fairness algorithm is used to arbitrate between the posted write queue and the delayed transaction queue.
4.4
DATA SYNCHRONIZATION
Data synchronization refers to the relationship between interrupt signaling and data delivery. The PCI Local Bus Specification, Revision 2.2, provides the following alternative methods for synchronizing data and interrupts: ! ! ! The device signaling the interrupt performs a read of the data just written (software). The device driver performs a read operation to any register in the interrupting device before accessing data written by the device (software). System hardware guarantees that write buffers are flushed before interrupts are forwarded.
The bridge does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written (or some other location along the same path), or from the device driver to one of the device registers.
5
ERROR HANDLING
The bridge checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, the bridge always tries to forward the existing parity condition on one bus to the other bus, along with address and data. The bridge always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions. To support error reporting on the PCI bus, the bridge implements the following: ! ! ! PERR# and SERR# signals on both the primary and secondary interfaces Primary status and secondary status registers The device-specific P_SERR# event disable register
This chapter provides detailed information about how the bridge handles errors. It also describes error status reporting and error operation disabling.
5.1
ADDRESS PARITY ERRORS
The bridge checks address parity for all transactions on both buses, for all address and all bus commands. When the bridge detects an address parity error on the primary interface, the following events occur: ! If the parity error response bit is set in the command register, the bridge does not claim the transaction with P_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, the bridge proceeds normally and accepts the transaction if it is directed to or across the bridge. The bridge sets the detected parity error bit in the status register. The bridge asserts P_SERR# and sets signaled system error bit in the status register, if both the following conditions are met: The SERR# enable bit is set in the command register. Page 44 of 90 JUNE 2004 - Revision 1.04
! ! !
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! The parity error response bit is set in the command register.
When the bridge detects an address parity error on the secondary interface, the following events occur: ! If the parity error response bit is set in the bridge control register, the bridge does not claim the transaction with S_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, the bridge proceeds normally and accepts transaction if it is directed to or across the bridge. The bridge sets the detected parity error bit in the secondary status register. The bridge asserts P_SERR# and sets signaled system error bit in status register, if both of the following conditions are met: The SERR# enable bit is set in the command register. The parity error response bit is set in the bridge control register.
! ! ! !
5.2
DATA PARITY ERRORS
When forwarding transactions, the bridge attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition. The following sections describe, for each type of transaction, the sequence of events that occurs when a parity error is detected and the way in which the parity condition is forwarded across the bridge.
5.2.1
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE
When the bridge detects a data parity error during a Type 0 configuration write transaction to the bridge configuration space, the following events occur: If the parity error response bit is set in the command register, the bridge asserts P_TRDY# and writes the data to the configuration register. The bridge also asserts P_PERR#. If the parity error response bit is not set, the bridge does not assert P_PERR#. The bridge sets the detected parity error bit in the status register, regardless of the state of the parity error response bit.
5.2.2
READ TRANSACTIONS
When the bridge detects a parity error during a read transaction, the target drives data and data parity, and the initiator checks parity and conditionally asserts PERR#. For downstream transactions, when the bridge detects a read data parity error on the secondary bus, the following events occur: ! ! ! Bridge asserts S_PERR# two cycles following the data transfer, if the secondary interface parity error response bit is set in the bridge control register. Bridge sets the detected parity error bit in the secondary status register. Bridge sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! ! Bridge forwards the bad parity with the data back to the initiator on the primary bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the data is discarded and the data with bad parity is not returned to the initiator. Bridge completes the transaction normally.
For upstream transactions, when the bridge detects a read data parity error on the primary bus, the following events occur: ! ! ! ! ! Bridge asserts P_PERR# two cycles following the data transfer, if the primary interface parity error response bit is set in the command register. Bridge sets the detected parity error bit in the primary status register. Bridge sets the data parity detected bit in the primary status register, if the primary interface parityerror-response bit is set in the command register. Bridge forwards the bad parity with the data back to the initiator on the secondary bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus, the data is discarded and the data with bad parity is not returned to the initiator. Bridge completes the transaction normally.
The bridge returns to the initiator the data and parity that was received from the target. When the initiator detects a parity error on this read data and is enabled to report it, the initiator asserts PERR# two cycles after the data transfer occurs. It is assumed that the initiator takes responsibility for handling a parity error condition; therefore, when the bridge detects PERR# asserted while returning read data to the initiator, the bridge does not take any further action and completes the transaction normally.
5.2.3
DELAYED WRITE TRANSACTIONS
When the bridge detects a data parity error during a delayed write transaction, the initiator drives data and data parity, and the target checks parity and conditionally asserts PERR#. For delayed write transactions, a parity error can occur at the following times: ! ! ! During the original delayed write request transaction When the initiator repeats the delayed write request transaction When the bridge completes the delayed write transaction to the target
When a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits, and data parity are all captured and a target retry is returned to the initiator. When the bridge detects a parity error on the write data for the initial delayed write request transaction, the following events occur: ! If the parity-error-response bit corresponding to the initiator bus is set, the bridge asserts TRDY# to the initiator and the transaction is not queued. If multiple data phases are requested, STOP# is also asserted to cause a target disconnect. Two cycles after the data transfer, the bridge also asserts PERR#. If the parity-error-response bit is not set, the bridge returns a target retry. It queues the transaction as usual. The bridge does not assert PERR#. In this case, the initiator repeats the transaction. The bridge sets the detected-parity-error bit in the status register corresponding to the initiator bus, regardless of the state of the parity-error-response bit.
! !
Note: If parity checking is turned off and data parity errors have occurred for queued or subsequent delayed write transactions on the initiator bus, it is possible that the initiator's re-attempts of the write transaction may not match the original queued delayed write information contained in the delayed Page 46 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION transaction queue. In this case, a master timeout condition may occur, possibly resulting in a system error (P_SERR# assertion). For downstream transactions, when the bridge is delivering data to the target on the secondary bus and S_PERR# is asserted by the target, the following events occur: ! ! The bridge sets the secondary interface data parity detected bit in the secondary status register, if the secondary parity error response bit is set in the bridge control register. The bridge captures the parity error condition to forward it back to the initiator on the primary bus.
Similarly, for upstream transactions, when the bridge is delivering data to the target on the primary bus and P_PERR# is asserted by the target, the following events occur: ! ! The bridge sets the primary interface data-parity-detected bit in the status register, if the primary parity-error-response bit is set in the command register. The bridge captures the parity error condition to forward it back to the initiator on the secondary bus.
A delayed write transaction is completed on the initiator bus when the initiator repeats the write transaction with the same address, command, data, and byte enable bits as the delayed write command that is at the head of the posted data queue. Note that the parity bit is not compared when determining whether the transaction matches those in the delayed transaction queues. Two cases must be considered: ! ! When parity error is detected on the initiator bus on a subsequent re-attempt of the transaction and was not detected on the target bus When parity error is forwarded back from the target bus
For downstream delayed write transactions, when the parity error is detected on the initiator bus and the bridge has write status to return, the following events occur: ! ! ! Bridge first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the primary interface parity-error-response bit is set in the command register. Bridge sets the primary interface parity-error-detected bit in the status register. Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and the bridge has write status to return, the following events occur: ! ! ! Bridge first asserts S_TRDY# and then asserts S_PERR# two cycles later, if the secondary interface parity-error-response bit is set in the bridge control register (offset 3Ch). Bridge sets the secondary interface parity-error-detected bit in the secondary status register. Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue.
For downstream transactions, where the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: ! ! ! Bridge asserts P_PERR# two cycles after the data transfer, if the following are both true: The parity-error-response bit is set in the command register of the primary interface. The parity-error-response bit is set in the bridge control register of the secondary interface. Page 47 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! Bridge completes the transaction normally.
For upstream transactions, when the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: ! ! ! ! Bridge asserts S_PERR# two cycles after the data transfer, if the following are both true: The parity error response bit is set in the command register of the primary interface. The parity error response bit is set in the bridge control register of the secondary interface. Bridge completes the transaction normally.
5.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when the bridge responds as a target, it detects a data parity error on the initiator (primary) bus and the following events occur: ! ! ! ! Bridge asserts P_PERR# two cycles after the data transfer, if the parity error response bit is set in the command register of primary interface. Bridge sets the parity error detected bit in the status register of the primary interface. Bridge captures and forwards the bad parity condition to the secondary bus. Bridge completes the transaction normally.
Similarly, during upstream posted write transactions, when the bridge responds as a target, it detects a data parity error on the initiator (secondary) bus, the following events occur: ! ! ! ! Bridge asserts S_PERR# two cycles after the data transfer, if the parity error response bit is set in the bridge control register of the secondary interface. Bridge sets the parity error detected bit in the status register of the secondary interface. Bridge captures and forwards the bad parity condition to the primary bus. Bridge completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target (secondary) bus by the target's assertion of S_PERR#, the following events occur: ! ! Bridge sets the data parity detected bit in the status register of secondary interface, if the parity error response bit is set in the bridge control register of the secondary interface. Bridge asserts P_SERR# and sets the signaled system error bit in the status register, if all the following conditions are met: ! ! ! ! ! The SERR# enable bit is set in the command register. The posted write parity error bit of P_SERR# event disable register is not set. The parity error response bit is set in the bridge control register of the secondary interface. The parity error response bit is set in the command register of the primary interface. Bridge has not detected the parity error on the primary (initiator) bus which the parity error is not forwarded from the primary bus to the secondary bus.
During upstream write transactions, when a data parity error is reported on the target (primary) bus by the target's assertion of P_PERR#, the following events occur: ! ! Bridge sets the data parity detected bit in the status register, if the parity error response bit is set in the command register of the primary interface. Bridge asserts P_SERR# and sets the signaled system error bit in the status register, if all the following conditions are met: Page 48 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
! ! ! !
The SERR# enable bit is set in the command register. The parity error response bit is set in the bridge control register of the secondary interface. The parity error response bit is set in the command register of the primary interface. Bridge has not detected the parity error on the secondary (initiator) bus, which the parity error is not forwarded from the secondary bus to the primary bus.
Assertion of P_SERR# is used to signal the parity error condition when the initiator does not know that the error occurred. Because the data has already been delivered with no errors, there is no other way to signal this information back to the initiator. If the parity error has forwarded from the initiating bus to the target bus, P_SERR# will not be asserted.
5.3
DATA PARITY ERROR REPORTING SUMMARY
In the previous sections, the responses of the bridge to data parity errors are presented according to the type of transaction in progress. This section organizes the responses of the bridge to data parity errors according to the status bits that the bridge sets and the signals that it asserts. Table 5-1 shows setting the detected parity error bit in the status register, corresponding to the primary interface. This bit is set when the bridge detects a parity error on the primary interface. Table 5-1. Setting the Primary Interface Detected Parity Error Bit
Primary Detected Parity Error Bit 0 0 1 0 1 0 0 0 1 0 0 0 X = don't care Transaction Type Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Bus Where Error Was Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary/ Secondary Parity Error Response Bits x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x
Table 5-2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when the bridge detects a parity error on the secondary interface. Table 5-2. Setting Secondary Interface Detected Parity Error Bit
Secondary Detected Parity Error Bit 0 1 0 0 0 0 0 1 0 0 0 Transaction Type Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Bus Where Error Was Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Primary/ Secondary Parity Error Response Bits x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x x/x
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Secondary Detected Parity Error Bit 1 X = don't care Transaction Type Delayed Write Direction Upstream Bus Where Error Was Detected Secondary Primary/ Secondary Parity Error Response Bits x/x
Table 5-3 shows setting data parity detected bit in the primary interface's status register. This bit is set under the following conditions: ! ! ! Bridge must be a master on the primary bus. The parity error response bit in the command register, corresponding to the primary interface, must be set. The P_PERR# signal is detected asserted or a parity error is detected on the primary bus.
Table 5-3. Setting Primary Interface Master Data Parity Error Detected Bit
Primary Data Parity Bit 0 0 1 0 0 0 1 0 0 0 1 0 X = don't care Transaction Type Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Bus Where Error Was Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary / Secondary Parity Error Response Bits x/x x/x 1/x x/x x/x x/x 1/x x/x x/x x/x 1/x x/x
Table 5-4 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the following conditions: ! ! ! The bridge must be a master on the secondary bus. The parity error response bit must be set in the bridge control register of secondary interface. The S_PERR# signal is detected asserted or a parity error is detected on the secondary bus.
Table 5-4. Setting Secondary Interface Master Data Parity Error Detected Bit
Secondary Detected Parity Detected Bit 0 1 0 0 0 1 0 0 0 1 0 0 X= don't care Transaction Type Read Read Read Read Posted Write Posted Write Posted Write Posted Write Delayed Write Delayed Write Delayed Write Delayed Write Direction Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Downstream Downstream Upstream Upstream Bus Where Error Was Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary / Secondary Parity Error Response Bits x/x x/1 x/x x/x x/x x/1 x/x x/x x/x x/1 x/x x/x
Table 5-5 shows assertion of P_PERR#. This signal is set under the following conditions:
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! ! ! The bridge is either the target of a write transaction or the initiator of a read transaction on the primary bus. The parity-error-response bit must be set in the command register of primary interface. The bridge detects a data parity error on the primary bus or detects S_PERR# asserted during the completion phase of a downstream delayed write transaction on the target (secondary) bus.
Table 5-5. Assertion of P_PERR#
P_PERR# Transaction Type Direction Bus Where Error Was Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary/ Secondary Parity Error Response Bits x/x x/x 1/x x/x 1/x x/x x/x x/x 1/x 1/1 x/x x/x
1 (de-asserted) Read Downstream 1 Read Downstream 0 (asserted) Read Upstream 1 Read Upstream 0 Posted Write Downstream 1 Posted Write Downstream 1 Posted Write Upstream 1 Posted Write Upstream 0 Delayed Write Downstream 02 Delayed Write Downstream 1 Delayed Write Upstream 1 Delayed Write Upstream X = don't care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 5-6 shows assertion of S_PERR# that is set under the following conditions: ! ! ! The bridge is either the target of a write transaction or the initiator of a read transaction on the secondary bus. The parity error response bit must be set in the bridge control register of secondary interface. Bridge detects a data parity error on the secondary bus or detects P_PERR# asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus.
Table 5-6. Assertion of S_PERR#
S_PERR# Transaction Type Direction Bus Where Error Was Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary/ Secondary Parity Error Response Bits x/x x/1 x/x x/x x/x x/x x/x x/1 x/x x/x 1/1 x/1
1 (de-asserted) Read Downstream 0 (asserted) Read Downstream 1 Read Upstream 1 Read Upstream 1 Posted Write Downstream 1 Posted Write Downstream 1 Posted Write Upstream 0 Posted Write Upstream 1 Delayed Write Downstream 1 Delayed Write Downstream 02 Delayed Write Upstream 0 Delayed Write Upstream X = don't care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Table 5-7 shows assertion of P_SERR#. This signal is set under the following conditions: ! ! ! The bridge has detected P_PERR# asserted on an upstream posted write transaction or S_PERR# asserted on a downstream posted write transaction. The bridge did not detect the parity error as a target of the posted write transaction. The parity error response bit on the command register and the parity error response bit on the bridge control register must both be set. Page 51 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION ! The SERR# enable bit must be set in the command register.
Table 5-7. Assertion of P_SERR# for Data Parity Errors
P_SERR# Transaction Type Direction Bus Where Error Was Detected Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary Secondary Primary / Secondary Parity Error Response Bits x/x x/x x/x x/x x/x 1/1 1/1 x/x x/x x/x x/x x/x
1 (de-asserted) Read Downstream 1 Read Downstream 1 Read Upstream 1 Read Upstream 1 Posted Write Downstream 02 (asserted) Posted Write Downstream 03 Posted Write Upstream 1 Posted Write Upstream 1 Delayed Write Downstream 1 Delayed Write Downstream 1 Delayed Write Upstream 1 Delayed Write Upstream X = don't care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 3 The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
5.4
SYSTEM ERROR (SERR#) REPORTING
The bridge uses the P_SERR# signal to report conditionally a number of system error conditions in addition to the special case parity error conditions described in Section 5.2.3. Whenever assertion of P_SERR# is discussed in this document, it is assumed that the following conditions apply: ! ! For the bridge to assert P_SERR# for any reason, the SERR# enable bit must be set in the command register. Whenever the bridge asserts P_SERR#, the bridge must also set the signaled system error bit in the status register.
In compliance with the PCI-to-PCI Bridge Architecture Specification, the bridge asserts P_SERR# when it detects the secondary SERR# input, S_SERR#, asserted and the SERR# forward enable bit is set in the bridge control register. In addition, the bridge also sets the received system error bit in the secondary status register. The bridge also conditionally asserts P_SERR# for any of the following reasons: ! ! ! ! ! ! ! Target abort detected during posted write transaction Master abort detected during posted write transaction Posted write data discarded after 224 (default) attempts to deliver (224 target retries received) Parity error reported on target bus during posted write transaction (see previous section) Delayed write data discarded after 224 (default) attempts to deliver (224 target retries received) Delayed read data cannot be transferred from target after 224 (default) attempts (224 target retries received) Master timeout on delayed transaction
The device-specific P_SERR# status register reports the reason for the assertion of P_SERR#. Most of these events have additional device-specific disable bits in the P_SERR# event disable register that make it possible to mask out P_SERR# assertion for specific events. The master timeout condition has a
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION SERR# enable bit for that event in the bridge control register and therefore does not have a devicespecific disable bit.
6
PCI BUS ARBITRATION
The bridge must arbitrate for use of the primary bus when forwarding upstream transactions. Also, it must arbitrate for use of the secondary bus when forwarding downstream transactions. The arbiter for the primary bus resides external to the bridge, typically on the motherboard. For the secondary PCI bus, the bridge implements an internal arbiter. This arbiter can be disabled, and an external arbiter can be used instead. This chapter describes primary and secondary bus arbitration.
6.1
PRIMARY PCI BUS ARBITRATION
The bridge implements a request output pin, P_REQ#, and a grant input pin, P_GNT#, for primary PCI bus arbitration. The bridge asserts P_REQ# when forwarding transactions upstream; that is, it acts as initiator on the primary PCI bus. As long as at least one pending transaction resides in the queues in the upstream direction, either posted write data or delayed transaction requests, the bridge keeps P_REQ# asserted. However, if a target retry, target disconnect, or a target abort is received in response to a transaction initiated by the bridge on the primary PCI bus, the bridge de-asserts P_REQ# for two PCI clock cycles. For all cycles through the bridge, P_REQ# is not asserted until the transaction request has been completely queued. When P_GNT# is asserted LOW by the primary bus arbiter after the bridge has asserted P_REQ#, the bridge initiates a transaction on the primary bus during the next PCI clock cycle. When P_GNT# is asserted to the bridge when P_REQ# is not asserted, the bridge parks P_AD, P_CBE, and P_PAR by driving them to valid logic levels. When the primary bus is parked at the bridge and the bridge has a transaction to initiate on the primary bus, the bridge starts the transaction if P_GNT# was asserted during the previous cycle.
6.2
SECONDARY PCI BUS ARBITRATION
The bridge implements an internal secondary PCI bus arbiter. This arbiter supports four external masters on the secondary bus in addition to the PI7C8148A. The secondary arbiter supports a programmable 2-level rotating algorithm. If the bridge detects that an initiator has failed to assert S_FRAME# after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter deasserts the grant. To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant signal in the same PCI cycle in which it de-asserts another. It de-asserts one grant and asserts the next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is busy, that is, S_FRAME# or S_IRDY# is asserted, the arbiter can be de-asserted one grant and asserted another grant during the same PCI clock cycle.
6.2.1
PREEMPTION
Preemption can be programmed to be either on or off, with the default to on (offset 4Ch, bit [31:28]). Time-to-preempt can be programmed to 0, 1, 2, 4, 8, 16, 32, or 64 (default is 0) clocks. If the current Page 53 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION master occupies the bus and other masters are waiting, the current master will be preempted by removing its grant (GNT#) after the next master waits for the time-to-preempt.
6.2.2
BUS PARKING
Bus parking refers to driving the AD[31:0], CBE[3:0], and PAR lines to a known value while the bus is idle. In general, the device implementing the bus arbiter is responsible for parking the bus or assigning another device to park the bus. A device parks the bus when the bus is idle, its bus grant is asserted, and the device's request is not asserted. The AD and CBE signals should be driven first, with the PAR signal driven one cycle later. The bridge parks the primary bus only when P_GNT# is asserted, P_REQ# is de-asserted, and the primary PCI bus is idle. When P_GNT# is de-asserted, the bridge 3-states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If the bridge is parking the primary PCI bus and wants to initiate a transaction on that bus, then the bridge can start the transaction on the next PCI clock cycle by asserting P_FRAME# if P_GNT# is still asserted. If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the PCI bus. That is, the bridge keeps the secondary bus grant asserted to a particular master until a new secondary bus request comes along. After reset, the bridge parks the secondary bus at itself until transactions start occurring on the secondary bus. Offset 48h, bit [1], can be set to 1 to park the secondary bus at PI7C8148A. By default, offset 48h, bit [1], is set to 0.
7
CLOCKS
This chapter provides information about the clocks.
7.1
PRIMARY CLOCK INPUTS
The bridge implements a primary clock input for the PCI interface. The primary interface is synchronized to the primary clock input, P_CLK, and the secondary interface is synchronized to the secondary clock. In synchronous mode, the secondary clock is derived internally from the primary clock, P_CLK. The bridge operates at a maximum frequency of 66 MHz.
7.2
SECONDARY CLOCK OUTPUTS
The bridge has 4 secondary clock outputs, S_CLKOUT[3:0] that can be used as clock inputs for up to four external secondary bus devices. The S_CLKOUT[3:0] outputs are derived from P_CLK. The secondary clock edges are delayed from P_CLK edges by a minimum of 0ns.
7.3
PCI CLOCKRUN
The bridge supports the PCI clock run protocol defined in the PCI Mobile Design Guide 1.0. P_CLKRUN# is set HIGH when the system's central resource initiates to stop the primary clock (P_CLK). The bridge will then signal that it allows the PCI clock to be stopped by keeping Page 54 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION P_CLKRUN# HIGH, or it will initiate P_CLK to remain running by driving P_CLKRUN# LOW for 2 clocks. After the 2 clocks have elapsed, the system's central resource will keep P_CLKRUN# LOW. There are 3 conditions where the bridge will keep the primary clock running: ! Bit [26] offset 6Ch is set to 1 ! There is a pending transaction running through the bridge ! A secondary device requires the clock The secondary clock run protocol is enabled by bit [25] offset 6Ch. The primary is responsible for the initiation of stopping or slowing down the secondary clock. The exception to this is if bit[28] offset 6Ch is set to 1. In this situation, the secondary clock will be stopped when the bus is idle and there are no other cycles from the primary bus.
8
GENERAL PURPOSE I/O INTERFACE
The PI7C8148A implements a 4-pin general purpose I/O interface. During normal operation, device specific configuration registers control the GPIO interface.
8.1
GPIO CONTROL REGISTERS
During normal operation, the GPIO Control Register (bits[23:8] offset C4h) controls the GPIO interface. Each GPIO pin can be configured to be either an input or an output pin. All GPIO pins can be read or written to at any time using either a type 0 configuration read or type 0 configuration write. Please see section 15.2.55 for more information on the GPIO Control Register.
9
EEPROM INTERFACE
The EEPROM interface consists of two pins: EECLK (EEPROM clock output) and EEPD (EEPROM bi-directional serial data). The bridge may control an ISSI IS24C02 or compatible part, which is organized into 256x8 bits. The EEPROM is used to initialize a select number of registers. This is accomplished after PRST# is deasserted, at which time the data from the EEPROM will be loaded. The EEPROM interface is organized into a 16-bit base, and the bridge supplies a 7-bit EEPROM word address. The bridge does not control the EEPROM address input. It can only access the EEPROM with address input set to 0.
9.1
AUTO MODE EEPROM ACCESS
The bridge may access the EEPROM in a WORD format by utilizing the auto mode through a hardware sequencer. The EEPROM start control, address, and read/write commands can be accessed through the configuration register. Before each access, the software should check the Start EEPROM bit before issuing the next start.
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9.2
EEPROM MODE AT RESET
During a reset, the bridge will autoload information/data from the EEPROM if the automatic load condition is met. The first offset in the EEPROM contains a signature. If the signature is recognized, the autoload will initiate right after the reset. During the autoload, the bridge will read sequential words from the EEPROM and write to the appropriate registers. Before the bridge registers can be accessed through the host, the autoload condition should be verified by reading bit[3] offset C8h (EEPROM Autoload Success). The host access is allowed only after the status of this bit becomes '1' which signifies that the autoload initialization sequence has completed successfully.
9.3
EEPROM DATA STRUCTURE
The bridge will access the EEPROM one WORD at a time. The bit order during the address phase is reverse that of the data phase. The data order starts with the MSB to the LSB during the address phase, but starts with the LSB to the MSB during the data phase.
9.4
EEPROM SPACE ADDRESS MAP
7-0 EEPROM Signature (1516h) Secondary Clock Enable Region Enable Subsystem Vendor ID Subsystem ID Test Mode / Chip Control / ISA Enable Arbiter Control Vendor ID Device ID Secondary Bus Arbiter Pre-emption Control Extended Chip Control Power Management Capability PM Data Register Reserved Port Option 15 - 8 WORD ADDRESS 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h
9.4.1
EEPROM CONTENT
Address 1:0 PCI Configuration Offset 8148 EEPROM Signature Autoload will only proceed if a value of 1516h is read on the first WORD loaded. Any other value read will disable the autoload. Region Enable - Enables or disables certain regions of the configuration space register from being loaded by the EEPROM Bit[0]: Reserved Bit[4:1]: 2 0000 - stop autoload at address 02h 0001 - stop autoload at address 04h 0011 - stop autoload at address 07h 0111 - stop autoload at address 11h 1111 - autoload all EEPROM loadable registers others - combinations are undefined Description
Bit[7:5]: Reserved
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PCI Configuration Offset 68h 68h - Bit[1:0] 68h - Bit[3:2] 68h - Bit[5:4] 68h - Bit[7:6] 68h - Bit[8] F0 - F1h F2 - F3h 40h 40h - Bit[16] 40h - Bit[17] 40h - Bit[18] 40h - Bit[19] 40h - Bit[25] C0h, 40h C0h - Bit[8] 40h - Bit[1] 40h - Bit[4] 9 40h - Bit[9] 40h - Bit[11:10]
Address
Description Secondary Clock Enable - Provides a means to disable the secondary clocks Bit[0]: set, S_CLKOUT[0] disable Bit[1]: set, S_CLKOUT[1] disable Bit[2]: set, S_CLKOUT[2] disable Bit[3]: set, S_CLKOUT[3] disable Bit[4]: set, S_CLKOUT[4] disable Bit[7:5]: Reserved Subsystem Vendor ID Subsystem ID Arbiter Control Bit[0]: set, S_REQ#[0] will be HIGH priority on the secondary bus Bit[1]: set, S_REQ#[1] will be HIGH priority on the secondary bus Bit[2]: set, S_REQ#[2] will be HIGH priority on the secondary bus Bit[3]: set, S_REQ#[3] will be HIGH priority on the secondary bus Bit[6:4]: Reserved Bit[7]: set, Bridge port will be HIGH priority on the secondary bus Test Mode / Chip Control / ISA Enable Bit[0]: set, legacy ISA I/O enable Bit[1]: Reserved Bit[2]: set, memory write disconnects at cache line aligned address boundary Bit[3]: set, bridge requests only 1 DWORD from the target and forwards read byte enable bits during upstream memory read Bit[4]: set, minimum 1 free space in data FIFO to accept memory burst write Bit[6:5]: Bridge Behavior Control 00 - Enable the out of transaction order between all 4 DTR requests 01 - Accept 3 DTR requests simultaneously and they may be out of transaction order 10 - Only the 2 DTR requests at the top of the 2 FIFO's may be allowed to out of transaction order 11 - No out of order transactions allowed for all DTR requests Bit[7]: set, 2 memory write transactions can be accepted at a time Vendor ID Device ID Extended Chip Control Bit[0]: set, memory read flow through enable Bit[1]: set, park to bridge port on secondary bus Bit[2]: set, downstream memory read prefetching dynamic control disable Bit[3]: set, upstream memory read prefetching dynamic control disable Bit[4]: set, memory read underflow control Bit[7:5]: Reserved Secondary Bus Arbiter Pre-emption Control Bit[3:0]: Reserved Bit[7:4]: Controls the number of clock cycles after FRAME is asserted before pre-emption is enabled 1xxx - Pre-emption off 0000 - Pre-emption enabled after 0 clock cycles after FRAME asserted 0001 - Pre-emption enabled after 1 clock cycle after FRAME asserted 0010 - Pre-emption enabled after 2 clock cycles after FRAME asserted 0011 - Pre-emption enabled after 4 clock cycles after FRAME asserted 0100 - Pre-emption enabled after 8 clock cycles after FRAME asserted 0101 - Pre-emption enabled after 16 clock cycles after FRAME asserted 0110 - Pre-emption enabled after 32 clock cycles after FRAME asserted 0111 - Pre-emption enabled after 64 clock cycles after FRAME asserted
3
5:4 7:6
8
0B:0A 0D:0C
40h - Bit[12] 00 - 01h 02 - 03h 48h 48h - Bit[0] 48h - Bit[1] 48h - Bit[2] 48h - Bit[3] 48h - Bit[4] 4Ch 4Ch - Bit[31:28]
0E
0F
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PCI Configuration Offset 80h 80h - Bit[18:16] 80h - Bit[21] 10 80h - Bit[25] 80h - Bit[26] 80h - Bit[31:27] 12 84h 13 84h - Bit[31:24] 74h Bit[15:8]: read only as Data Register Port Option Register Bit[0]: Reserved Bit[1]: set, primary memory read command alias enable Bit[2]: set, primary memory write command alias enable Bit[3]: set, secondary memory read command alias enable Bit[4]: set, secondary memory write command alias enable Bit[5]: set, primary memory read line/multiple alias enable Bit[6]: set, secondary memory read line/multiple alias enable Bit[7]: set, primary memory write & invalidate command alias disable Bit[8]: set, secondary memory write & invalidate command alias disable Bit[9]: set, enable long request for LOCK cycle Bit[10]: set, enable secondary to hold request longer Bit[11]: set, enable primary to hold request longer Bit[15:12]: Reserved
Address
Description Power Management Capability Bit[2:0]: read only as 010 to indicate the device is compliant to Revision 1.1 of PCI Power Management Interface Specifications Bit[4:3]: Reserved Bit[5]: read only as 0 to indicate bridge does not have device specific utilization requirements Bit[8:6]: Reserved Bit[9]: read only as 1 to indicate bridge supports the D1 power management state Bit[10]: read only as 1 to indicate bridge supports the D2 power management state Bit[14:11]: read only as 0 to indicate bridge does not support the PME# pin Bit[15]: Reserved Reserved Power Management Data
14
10
COMPACT PCI HOT SWAP
Compact PCI (cPCI) Hot Swap (PICMG 2.1, R1.0) defines a process for installing and removing PCI boards form a Compact PCI system without powering down the system. The PI7C8148A is Hot Swap Friendly silicon that supports all the cPCI Hot Swap Capable features and adds support for Software Connection Control. Being Hot Swap Friendly, the bridge supports the following: ! ! ! ! ! ! Compliance with PCI Specification 2.2 Tolerates VCC from Early Power Asynchronous Reset Tolerates Precharge Voltage I/O Buffers Meet Modified V/I Requirements Limited I/O Pin Leakage at Precharge Voltage
The bridge provides two pins to support hot swap: ENUM# and LOO. The ENUM# output indicates to the system that an insertion event occurred or that an extraction is about to occur. The LOO output lights an LED to signal insertion- and removal-ready status.
11
PCI POWER MANAGEMENT
The bridge incorporates functionality that meets the requirements of the PCI Power Management Specification, Revision 1.1. These features include: Page 58 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
! ! ! !
PCI Power Management registers using the Enhanced Capabilities Port (ECP) address mechanism Support for D0, D3hot, and D3cold power management states Support for D0, D1, D2, D3hot , and D3cold power management states for devices behind the bridge Support of the B2 secondary bus power state when in the D3hot power management state
Table 11-1 shows the states and related actions that the bridge performs during power management transitions. (No other transactions are permitted.) Table 11-1. Power Management Transitions
Current Status D0 D0 D0 D0 D3hot D3hot D3cold Next State D3cold D3hot D2 D1 D0 D3cold D0 Action Power has been removed from bridge. A power-up reset must be performed to bring bridge to D0. If enabled to do so by the BPCCE pin, bridge will disable the secondary clocks and drive them LOW. Unimplemented power state. bridge will ignore the write to the power state bits (power state remains at D0). Unimplemented power state. bridge will ignore the write to the power state bits (power state remains at D0). Bridge enables secondary clock outputs and performs an internal chip reset. Signal S_RST# will not be asserted. All registers will be returned to the reset values and buffers will be cleared. Power has been removed from bridge. A power-up reset must be performed to bring bridge to D0. Power-up reset. Bridge performs the standard power-up reset functions as described in Section 12.
PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME# signals do not pass through PCI-to-PCI bridges.
12
RESET
This chapter describes the primary interface, secondary interface, and chip reset mechanisms.
12.1 PRIMARY INTERFACE RESET
The bridge has a reset input, P_RST#. When P_RST# is asserted, the following events occur: ! ! ! Bridge immediately tri-states all primary and secondary PCI interface signals. Bridge performs a chip reset. Registers that have default values are reset.
P_RST# asserting and de-asserting edges can be asynchronous to P_CLK and S_CLKOUT. The bridge is not accessible during P_RST#. After P_RST# is de-asserted, the bridge remains inaccessible for 16 PCI clocks before the first configuration transaction can be accepted.
12.2 SECONDARY INTERFACE RESET
The bridge is responsible for driving the secondary bus reset signals, S_RST#. The bridge asserts S_RST# when any of the following conditions are met: Page 59 of 90 JUNE 2004 - Revision 1.04
PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Signal P_RST# is asserted. Signal S_RST# remains asserted as long as P_RST# is asserted and does not de-assert until P_RST# is de-asserted. The secondary reset bit in the bridge control register is set. Signal S_RST# remains asserted until a configuration write operation clears the secondary reset bit. S_RST# pin is asserted. When S_RST# is asserted, the bridge immediately 3-states all the secondary PCI interface signals associated with the secondary port. The S_RST# in asserting and de-asserting edges can be asynchronous to P_CLK. When S_RST# is asserted, all secondary PCI interface control signals, including the secondary grant outputs, are immediately 3-stated. Signals S1_AD, S1_CBE#[3:0], S_PAR are driven low for the duration of S_RST# assertion. All posted write and delayed transaction data buffers are reset. Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded. When S_RST# is asserted by means of the secondary reset bit, the bridge remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface.
12.3 CHIP RESET
The chip reset bit in the diagnostic control register can be used to reset the bridge and the secondary bus. When the chip reset bit is set, all registers and chip state are reset and all signals are tristated. S_RST# is asserted and the secondary reset bit is automatically set. S_RST# remains asserted until a configuration write operation clears the secondary reset bit and the serial clock mask has been shifted in. Within 20 PCI clock cycles after completion of the configuration write operation, the bridge's reset bit automatically clears and the bridge is ready for configuration. During reset, the bridge is inaccessible.
13
SUPPORTED COMMANDS
The PCI command set is given below for the primary and secondary interfaces.
13.1 PRIMARY INTERFACE
P_CBE [3:0] 0000 0001 0010 0011 0100 0101 0110 Command Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Action Ignore Do not claim. Ignore. 1. If address is within pass through I/O range, claim and pass through. 2. Otherwise, do not pass through and do not claim for internal access. Same as I/O Read. --------1. If address is within pass through memory range, claim and pass through.
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P_CBE [3:0] Command Action 2. If address is within pass through memory mapped I/O range, claim and pass through. 0111 1000 1001 1010 Memory Write Reserved Reserved Configuration Read 3. Otherwise, do not pass through and do not claim for internal access. Same as Memory Read. --------Type 0 Configuration Read: If the bridge's IDSEL line is asserted, perform function decode and claim if target function is implemented. Otherwise, ignore. If claimed, permit access to target function's configuration registers. Do not pass through under any circumstances. Type 1 Configuration Read: 1. If the target bus is the bridge's secondary bus: claim and pass through as a Type 0 Configuration Read. 2. If the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through as a Type 1 Configuration Read. 1011 Configuration Write 3. Otherwise, ignore. Type 0 Configuration Write: same as Configuration Read. Type 1 Configuration Write (not special cycle request): 1. If the target bus is the bridge's secondary bus: claim and pass through as a Type 0 Configuration Write 2. If the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through unchanged as a Type 1 Configuration Write. 3. Otherwise, ignore. Configuration Write as Special Cycle Request (device = 1Fh, function = 7h) 1. If the target bus is the bridges secondary bus: claim and pass through as a special cycle. 2. If the target bus is a subordinate bus that exists behind the bridge (but not equal to the secondary bus): claim and pass through unchanged as a type 1 Configuration Write. 1100 1101 1110 1111 Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate 3. Otherwise ignore Same as Memory Read Supported Same as Memory Read Same as Memory Read
13.2 SECONDARY INTERFACE
S_CBE[3:0] 0000 0001 0010 0011 0100 0101 0110 Command Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Action Ignore Do not claim. Ignore. Same as Primary Interface Same as I/O Read. --------Same as Primary Interface
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S_CBE[3:0] 0111 1000 1001 1010 1011 Command Memory Write Reserved Reserved Configuration Read Configuration Write Action Same as Memory Read. --------Ignore I. Type 0 Configuration Write: Ignore II. Type 1 Configuration Write (not special cycle request):Ignore III. Configuration Write as Special Cycle Request (device = 1Fh, function = 7h): 1. If the target bus is the bridge's primary bus: claim and pass through as a Special Cycle 2. If the target bus is neither the primary bus nor is it in range of buses defined by the bridge's secondary and subordinate bus registers: claim and pass through unchanged as a Type 1 Configuration Write. 3. If the target bus is not the bridge's primary bus, but is in range of buses defined by the bridge's secondary and subordinate bus registers: ignore. Same as Memory Read Supported Same as Memory Read Same as Memory Read
1100 1101 1110 1111
Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate
14
BRIDGE BEHAVIOR
A PCI cycle is initiated by asserting the FRAME# signal. In a bridge, there are a number of possibilities. Those possibilities are summarized in the table below:
14.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES
Initiator Master on Primary Target Target on Primary Response Bridge does not respond. It detects this situation by decoding the address as well as monitoring the P_DEVSEL# for other fast and medium devices on the Primary Port. Bridge asserts P_DEVSEL#, terminates the cycle normally if it is able to be posted, otherwise return with a retry. It then passes the cycle to the appropriate port. When the cycle is complete on the target port, it will wait for the initiator to repeat the same cycle and end with normal termination. Bridge does not respond and the cycle will terminate as master abort. Bridge does not respond. Bridge asserts S_DEVSEL#, terminates the cycle normally if it is able to be posted, otherwise returns with a retry. It then passes the cycle to the appropriate port. When cycle is complete on the target port, it will wait for the initiator to repeat the same cycle and end with normal termination. Bridge does not respond.
Master on Primary
Target on Secondary
Master on Primary Master on Secondary Master on Secondary
Target not on Primary nor Secondary Port Target on the same Secondary Port Target on Primary or the other Secondary Port
Master on Secondary
Target not on Primary nor the other Secondary Port
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14.2 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER)
14.2.1 MASTER ABORT
Master abort indicates that when the bridge acts as a master and receives no response (i.e., no target asserts DEVSEL# or S_DEVSEL#) from a target, the bridge de-asserts FRAME# and then deasserts IRDY#.
14.2.2 PARITY AND ERROR REPORTING
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR, and S_PAR signals. Parity should be even (i.e. an even number of`1's) across AD, CBE, and PAR. Parity information on PAR is valid the cycle after AD and CBE are valid. For reads, even parity must be generated using the initiators CBE signals combined with the read data. Again, the PAR signal corresponds to read data from the previous data phase cycle.
14.2.3 REPORTING PARITY ERRORS
For all address phases, if a parity error is detected, the error should be reported on the P_SERR# signal by asserting P_SERR# for one cycle and then 3-stating two cycles after the bad address. P_SERR# can only be asserted if bit 6 and 8 in the Command Register are both set to 1. For write data phases, a parity error should be reported by asserting the P_PERR_L signal two cycles after the data phase and should remain asserted for one cycle when bit 6 in the Command register is set to a 1. The target reports any type of data parity errors during write cycles, while the master reports data parity errors during read cycles. Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim the bus (P_DEVSEL# remains inactive) and the cycle will then terminate with a Master Abort. When the bridge is acting as master, a data parity error during a read cycle results in the bridge master initiating a Master Abort.
14.2.4 SECONDARY IDSEL MAPPING
When the bridge detects a Type 1 configuration transaction for a device connected to the secondary, it translates the Type 1 transaction to Type 0 transaction on the downstream interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11] as a device number. This is translated to S_AD[31:16] by the bridge.
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15
CONFIGURATION REGISTERS
PCI configuration defines a 64-byte DWORD to define various attributes of PI7C8148A as shown below.
15.1 REGISTER TYPES
REGISTER TYPE RO RW RWC RWR RWS DEFINITION Read Only Read / Write Read / Write 1 to Clear Read / Write 1 to Reset (for about 20 clocks) Read / Write 1 to Set
15.2 CONFIGURATION REGISTER
31 - 24 23 - 16 Device ID Primary Status Class Code 15 - 8 Vendor ID Command 7-0 DWORD ADDRESS 00h 04h 08h 0Ch 10h - 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch 50h - 60h 64h 68h 6Ch 70h 74h 78h - 7Ch 80h 84h 88h 8Ch 90h 94h 98h - 9Fh
Revision ID Primary Latency Cache Line Size Timer Reserved Secondary Latency Subordinate Bus Secondary Bus Primary Bus Timer Number Number Number Secondary Status I/O Limit Address I/O Base Address Memory Limit Address Memory Base Address Prefetchable Memory Limit Address Prefetchable Memory Base Address Prefetchable Memory Base Address Upper 32-bit Prefetchable Memory Limit Address Upper 32-bit I/O Limit Address Upper 16-bit I/O Base Address Upper 16-bit Reserved Capability Pointer Reserved Bridge Control Interrupt Pin Reserved Arbiter Control Diagnostic / Chip Control Reserved Reserved Extended Chip Control Secondary Bus Reserved Arbiter Preemption Control Reserved P_SERR# Event Reserved Disable Reserved P_SERR# Status Secondary Clock Control CLKRUN Reserved Reserved Reserved Port Option Reserved Power Management Capabilities Next Item Pointer Capability ID PPB Support PM Data Power Management Data Extensions Secondary Master Timeout Counter Primary Master Timeout Counter Reserved Reserved HSCSR Next Item Pointer Capability ID Reserved Hot Swap Switch Reserved Reserved Header Type
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VPD Register Next Item Pointer VPD Data Register Reserved Miscellaneous Control GPIO Control EEPROM Address Reserved Reserved Subsystem ID Reserved Subsystem Vendor ID Capability ID A0h A4h A8h - BFh C0h C4h C8h CCh D0h - Efh F0h F4h - FFh
Reserved Reserved EEPROM Data EEPROM Test Register
Reserved Reserved EEPROM Control
15.2.1 VENDOR ID REGISTER - OFFSET 00h
Bit 15:0 Function Vendor ID Type RO Description Identifies Pericom as the vendor of this device. Hardwired as 12D8h.
15.2.2 DEVICE ID REGISTER - OFFSET 00h
Bit 31:16 Function Device ID Type RO Description Identifies this device as the PI7C8148A. Reset to 8148h.
15.2.3 COMMAND REGISTER - OFFSET 04h
Bit 0 Function I/O Space Enable Type RW Description 0: ignore I/O transactions on the primary interface 1: enable response to I/O transactions on the primary interface Reset to 0 0: ignore memory transactions on the primary interface 1 Memory Space Enable RW 1: enable response to memory transactions on the primary interface Reset to 0 0: do not initiate memory or I/O transactions on the primary interface and disable response to memory and I/O transactions on the secondary interface 2 Bus Master Enable RW 1: enables bridge to operate as a master on the primary interfaces for memory and I/O transactions forwarded from the secondary interface Reset to 0 No special cycles defined. Bit is defined as read only and returns 0 when read Bridge does not generate memory write and invalidate transactions except for forwarding a transaction for another master. Bit is implemented as read only and returns 0 when read (unless forwarding a transaction for another master) 0: ignore VGA palette accesses on the primary RW 1: enable positive decoding response to VGA palette writes on the primary interface with I/O address bits AD[9:0] equal to 3C6h, 3C8h, and 3C9h (inclusive of ISA alias; AD[15:10] are not decoded and may be any value) Reset to 0 0: bridge may ignore any parity errors that it detects and continue normal
3
Special Cycle Enable Memory Write And Invalidate Enable
RO
4
RO
5
VGA Palette Snoop Enable
6
Parity Error
RW
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Bit Function Response Type Description operation 1: bridge must take its normal action when a parity error is detected Reset to 0 Read as 0 to indicate PI7C8148A does not perform address / data stepping. RO Reset to 0 0: disable the P_SERR# driver RW 1: enable the P_SERR# driver Reset to 0 0: disable bridge's ability to initiate fast back-to-back transactions on the primary 9 15:10 Fast Back-toBack Enable Reserved RW RO 1: enable bridge's ability to initiate fast back-to-back transactions on the primary Reset to 0 Returns 000000 when read
7
Wait Cycle Control P_SERR# enable
8
15.2.4 PRIMARY STATUS REGISTER - OFFSET 04h
Bit 19:16 20 Function Reserved Capabilities List 66MHz Capable Reserved Fast Back-toBack Capable Data Parity Error Detected Type RO RO Description Reset to 0000 Set to 1 to enable support for the capability list (offset 34h is the pointer to the data structure) Reset to 1 Set to 1 to indicate the primary may be run at 66MHz operation Reset to 1 Reset to 0 Set to 1 to enable decoding of fast back-to-back transactions on the primary interface to different targets Reset to 1 0: No parity error detected on the primary (bridge is the primary bus master) 1: Parity error detected on the primary (bridge is the primary bus master) 26:25 DEVSEL# timing RO Reset to 0 DEVSEL# timing (medium decoding) 01: medium DEVSEL# decoding 27 28 Signaled Target Abort Received Target Abort Received Master Abort Signaled System Error Detected Parity Error RWC RWC Reset to 01 Set to 1 (by a target device) whenever a target abort cycle occurs Reset to 0 Set to 1 (by a master device) whenever transactions are terminated with target aborts Reset to 0 Set to 1 (by a master) when transactions are terminated with Master Abort Reset to 0 Set to 1 when P_SERR# is asserted Reset to 0 Set to 1 when address or data parity error is detected on the primary interface Reset to 0
21 22 23
RO RO RO
24
RWC
29 30 31
RWC RWC RWC
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15.2.5 REVISION ID REGISTER - OFFSET 08h
Bit 7:0 Function Revision Type RO Description Indicates revision number of device. Hardwired to 00h
15.2.6 CLASS CODE REGISTER - OFFSET 08h
Bit 15:8 23:16 31:24 Function Programming Interface Sub-Class Code Base Class Code Type RO RO RO Description Read as 00h to indicate no programming interfaces have been defined for PCI-toPCI bridges Read as 04h to indicate device is PCI-to-PCI bridge Read as 06h to indicate device is a bridge device
15.2.7 CACHE LINE REGISTER - OFFSET 0Ch
Bit 7:0 Function Cache Line Size Type RW Description Designates the cache line size for the system and is used when terminating memory write and invalidate transactions and when prefetching memory read transactions. Only cache line sizes (in units of 4-byte) which are a power of two are valid (only one bit can be set in this register; only 00h, 01h, 02h, 04h, 08h, and 10h are valid values). Reset to 0
15.2.8 PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch
Bit 15:8 Function Primary Latency timer Type RW Description This register sets the value for the Master Latency Timer, which starts counting when the master asserts FRAME#. Reset to 0
15.2.9 HEADER TYPE REGISTER - OFFSET 0Ch
Bit 23:16 Function Header Type Type RO Description Read as 01h to indicate that the register layout conforms to the standard PCI-toPCI bridge layout.
15.2.10 PRIMARY BUS NUMBER REGISTER - OFFSET 18h
Bit 7:0 Function Primary Bus Number Type RW Description Indicates the number of the PCI bus to which the primary interface is connected. The value is set in software during configuration. Reset to 0
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15.2.11 SECONDARY BUS NUMBER REGISTER - OFFSET 18h
Bit 15:8 Function Secondary Bus Number Type RW Description Indicates the number of the PCI bus to which the secondary interface is connected. The value is set in software during configuration. Reset to 0
15.2.12 SUBORDINATE BUS NUMBER REGISTER - OFFSET 18h
Bit 23:16 Function Subordinate Bus Number Type RW Description Indicates the number of the PCI bus with the highest number that is subordinate to the bridge. The value is set in software during configuration. Reset to 0
15.2.13 SECONDARY LATENCY TIMER REGISTER - OFFSET 18h
Bit 31:24 Function Secondary Latency Timer Type RW Description Latency timer for secondary. Indicates the number of PCI clocks from the assertion of S_FRAME# to the expiration of the timer when the bridge is acting as a master on the secondary. 0: Bridge ends the transaction after the first data transfer when the bridge's secondary bus grant has been deasserted, with the exception of memory write and invalidate transactions. Reset to 0
15.2.14 I/O BASE ADDRESS REGISTER - OFFSET 1Ch
Bit 3:0 7:4 Function 32-bit Indicator I/O Base Address [15:12] Type RO RW Description Read as 01h to indicate 32-bit I/O addressing Defines the bottom address of the I/O address range for the bridge to determine when to forward I/O transactions from one interface to the other. The upper 4 bits correspond to address bits [15:12] and are writable. The lower 12 bits corresponding to address bits [11:0] are assumed to be 0. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O base address upper 16 bits address register Reset to 0
15.2.15 I/O LIMIT ADDRESS REGISTER - OFFSET 1Ch
Bit 11:8 15:12 Function 32-bit Indicator I/O Limit Address [15:12] Type RO RW Description Read as 01h to indicate 32-bit I/O addressing Defines the top address of the I/O address range for the bridge to determine when to forward I/O transactions from one interface to the other. The upper 4 bits correspond to address bits [15:12] and are writable. The lower 12 bits corresponding to address bits [11:0] are assumed to be FFFh. The upper 16 bits corresponding to address bits [31:16] are defined in the I/O limit address upper 16 bits address register Reset to 0
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15.2.16 SECONDARY STATUS REGISTER - OFFSET 1Ch
Bit 20:16 21 Function Reserved 66MHz Capable Reserved Fast Back-toBack Capable Data Parity Error Detected DEVSEL_L timing Type RO RO Description Reset to 0 Set to 1 to indicate bridge is capable of 66MHz operation on the secondary interface Reset to 1 Reset to 0 Set to 1 to indicate bridge is capable of decoding fast back-to-back transactions on the secondary interface to different targets Reset to 1 Set to 1 when S_PERR# is asserted and bit 6 of command register is set RWC Reset to 0 DEVSEL# timing (medium decoding) RO 01: medium DEVSEL# decoding Reset to 01 Set to 1 (by a target device) whenever a target abort cycle occurs on its secondary interface Reset to 0 Set to 1 (by a master device) whenever transactions on its secondary interface are terminated with target abort Reset to 0 Set to 1 (by a master) when transactions on its secondary interface are terminated with Master Abort Reset to 0 Set to 1 when S_SERR# is asserted RWC Reset to 0 Set to 1 when address or data parity error is detected on the secondary interface RWC Reset to 0
22 23
RO RO
24
26:25
27
Signaled Target Abort Received Target Abort Received Master Abort Received System Error Detected Parity Error
RWC
28
RWC
29
RWC
30 31
15.2.17 MEMORY BASE ADDRESS REGISTER - OFFSET 20h
Bit 3:0 15:4 Function Reserved Memory Base Address [15:4] Type RO RW Description Reset to 0 Defines the bottom address of an address range for the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits corresponding to address bits [19:0] are assumed to be 0. Reset to 0
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15.2.18 MEMORY LIMIT ADDRESS REGISTER - OFFSET 20h
Bit 19:16 31:20 Function Reserved Memory Limit Address [31:20] Type RO RW Description Reset to 0 Defines the top address of an address range for the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits corresponding to address bits [19:0] are assumed to be FFFFFh.
15.2.19 PREFETCHABLE MEMORY BASE ADDRESS REGISTER - OFFSET 24h
Bit 3:0 Function 64-bit addressing Type RO Description Indicates 64-bit addressing 0001: 64-bit addressing 15:4 Prefetchable Memory Base Address [31:20] RW Reset to 1 Defines the bottom address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits are assumed to be 0. The memory base register upper 32 bits contains the upper half of the base address.
15.2.20 PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER - OFFSET 24h
Bit 19:16 Function 64-bit addressing Type RO Description Indicates 64-bit addressing 0001: 64-bit addressing 31:20 Prefetchable Memory Limit Address [31:20] RW Reset to 1 Defines the top address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits are assumed to be FFFFFh. The memory limit upper 32 bits register contains the upper half of the limit address.
15.2.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER - OFFSET 28h
Bit 31:0 Function Prefetchable Memory Base Address, Upper 32-bits [63:32] Type RW Description Defines the upper 32-bits of a 64-bit bottom address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. Reset to 0
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15.2.22 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER - OFFSET 2Ch
Bit 31:0 Function Prefetchable Memory Limit Address, Upper 32-bits [63:32] Type RW Description Defines the upper 32-bits of a 64-bit top address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. Reset to 0
15.2.23 I/O BASE ADDRESS UPPER 16-BITS REGISTER - OFFSET 30h
Bit 15:0 Function I/O Base Address, Upper 16-bits [31:16] Type RW Description Defines the upper 16-bits of a 32-bit bottom address of an address range for the bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0
15.2.24 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER - OFFSET 30h
Bit 31:16 Function I/O Limit Address, Upper 16-bits [31:16] Type RW Description Defines the upper 16-bits of a 32-bit top address of an address range for the bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0
15.2.25 CAPABILITY POINTER REGISTER - OFFSET 34h
Bit 7:0 Function Capability Pointer Type RO Description Pointer points to the PCI power management registers (80h). Reset to 80h
15.2.26 INTERRUPT LINE REGISTER - OFFSET 3Ch
Bit 7:0 Function Interrupt Line Type RW Description Bridge does not implement an interrupt signal, so POST programs FFh to this register.
15.2.27 INTERRUPT PIN REGISTER - OFFSET 3Ch
Bit 15:8 Function Interrupt Pin Type RO Description Bridge does not implement interrupt signal pins. Reset to 0
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15.2.28 BRIDGE CONTROL REGISTER - OFFSET 3Ch
Bit 16 Function Parity Error Response Type RW Description 0: ignore address and data parity errors on the secondary interface 1: enable parity error reporting and detection on the secondary interface 17 S_SERR# enable RW Reset to 0 0: disable the forwarding of S_SERR# to primary interface 1: enable the forwarding of S_SERR# to primary interface 18 ISA enable RW Reset to 0 Modifies the bridge's response to ISA I/O addresses, applying only to those addresses falling within the I/O base and limit address registers and within the first 64KB of PCI I/O space. 0: forward all I/O addresses in the range defined by the I/O base and I/O limit registers 1: blocks forwarding of ISA I/O addresses in the range defined by the I/O base and I/O limit registers that are in the first 64KB of I/O space that address the last 768 bytes in each 1KB block. Secondary I/O transactions are forwarded upstream if the address falls within the last 768 bytes in each 1KB block 19 VGA enable RW Reset to 0 0: does not forward VGA compatible memory and I/O addresses from primary to secondary 1: forward VGA compatible memory and I/O addresses from primary to secondary regardless of other settings 20 21 Reserved Master Abort Mode R/O RW Reset to 0 Reserved. Returns 0 when read. Reset to 0 0: does not report master aborts (returns FFFF_FFFFh on reads and discards data on writes) 1: reports master aborts by signaling target abort if possible or by the assertion of P_SERR# if enabled 22 Secondary Interface Reset RW Reset to 0 0: does not force the assertion of S_RESET# pin 1: forces the assertion of S_RESET# 23 Fast Back-toBack Enable RW Reset to 0 Controls bridge's ability to generate fast back-to-back transactions to different devices on the secondary interface. 0: does not generate fast back-to-back transactions on the secondary 1: enables fast back-to-back transaction generation on the secondary 24 Primary Master Timeout R/W Reset to 0 Determines the maximum number of PCI clock cycles the bridge waits for an initiator on the primary interface to repeat a delayed transaction request. 0: Primary discard timer counts 215 PCI clock cycles. 1: Primary discard timer counts 210 PCI clock cycles. Reset to 0
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Bit 25 Function Secondary Master Timeout Type RW Description Determines the maximum number of PCI clock cycles the bridge waits for an initiator on the secondary interface to repeat a delayed transaction request. 0: Secondary discard timer counts 215 PCI clock cycles. 1: Secondary discard timer counts 210 PCI clock cycles. 26 Master Timeout Status Discard Timer P_SERR# enable RWC Reset to 0 This bit is set to 1 when either the primary master timeout counter or secondary master timeout counter expires. Reset to 0 This bit is set to 1 and P_SERR# is asserted when either the primary discard timer or the secondary discard timer expire. 0: P_SERR# is not asserted on the primary interface as a result of the expiration of either the Primary Discard Timer or the Secondary Discard Timer. 1: P_SERR# is asserted on the primary interface as a result of the expiration of either the Primary Discard Timer or the Secondary Discard Timer. 31-28 Reserved RO Reset to 0 Reserved. Returns 0 when read. Reset to 0.
27
RW
15.2.29 DIAGNOSTIC/CHIP CONTROL REGISTER - OFFSET 40h
Bit 0 1 Function Reserved Memory Write Disconnect Type RO RW Description Reserved. Returns 0 when read. Reset to 0 0: Memory write disconnects at 4KB aligned address boundary 1: Memory write disconnects at cache line aligned address boundary 3:2 4 Reserved Secondary Bus Prefetch Disable RO RW Reset to 0 Reserved. Returns 00 when read. Reset to 00 0: Bridge prefetches and does not forward byte enable bits during upstream memory read 1: Bridge requests only 1 DWORD from the target and forwards read byte enable bits during upstream memory read 7:5 8 Reserved Chip Reset RO RWR Reset to 0 Reserved. Returns 00 when read. Reset to 00 0: Bridge is ready for operation 1: Forces Bridge to do a reset 9 Test Mode 1: Bridge behavior control Test Mode 2: Bridge behavior control RW Reset to 0 0: Minimum 8 free spaces in data FIFO to accept memory burst writes 1: Minimum 1 free space in data FIFO to accept memory burst writes RW Reset to 0 00: Enable the out of transaction order between all 4 DTR requests 01: Accept 3 DTR requests simultaneously and they may be out of transaction order 10: Only the 2 DTR requests at the top of the 2 FIFO's may be allowed to be out of transaction order 11: No out of order transactions allowed for all DTR requests. Reset to 00
11:10
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Bit 12 Function Test Mode 3: Bridge behavior control Reserved Type RW Description 0: 4 memory write transactions may be accepted at a time 1: 2 memory write transactions may be accepted at a time RO Reset to 0 Reserved. Returns 000 when read. Reset to 000
15:13
15.2.30 ARBITER CONTROL REGISTER - OFFSET 40h
Bit 16 Function S_REQ#[0] priority Type RW Description S_REQ#[0] priority on secondary bus 0: low priority 1: high priority 17 S_REQ#[1] priority RW Reset to 0 S_REQ#[1] priority on secondary bus 0: low priority 1: high priority 18 S_REQ#[2] priority RW Reset to 0 S_REQ#[2] priority on secondary bus 0: low priority 1: high priority 19 S_REQ#[3] priority RW Reset to 0 S_REQ#[3] priority on secondary bus 0: low priority 1: high priority 24:20 25 Reserved HPG_SM, bridge port RO RW Reset to 0 Reserved. Returns 00000 when read. Reset to 00000 Secondary REQ priority 0: low priority 1: high priority 31:26 Reserved RO Reset to 1 Reserved. Returns 0 when read. Reset to 0
15.2.31 EXTENDED CHIP CONTROL REGISTER - OFFSET 48h
Bit 0 Function Memory Read Flow Through Enable Type RW Description 0: Disable flow through during a memory read transaction 1: Enable flow through during a memory read transaction Reset to 0
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Bit Function Type Description Controls bus arbiter's park function 0: Park to last master 1 Park RW 1: Park to the bridge - secondary port Reset to 0 Controls the downstream (P to S) memory read line and memory read multiple prefetching dynamic control Downstream Dynamic Prefetching Control 0: Enable the downstream memory read line and memory read multiple prefetching dynamic control 1: Disable the downstream memory read line and memory read multiple prefetching dynamic control Reset to 0 Controls the upstream (S to P) memory read line and memory read multiple prefetching dynamic control Upstream Dynamic Prefetching Control 0: Enable the upstream memory read line and memory read multiple prefetching dynamic control 1: Disable the upstream memory read line and memory read multiple prefetching dynamic control Reset to 0 Ability to control bridge's behavior when the data buffer is empty Memory Read Data Buffer Control 0: start returning memory read data right away and inserts wait states if the data buffer is empty RW 1: start returning memory read data after 1 cache line of data and disconnects the master if the data buffer is empty RO Reset to 0 Reserved. Returns 0 when read. Reset to 0
2
RW
3
RW
4
15:5
Reserved
15.2.32 SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER - OFFSET 4Ch
Bit Function Type Description Controls the number of clock cycles after frame is asserted before preemption is enabled. 1xxx: Preemption off 0000: Preemption enabled after 0 clock cycles after FRAME asserted 0001: Preemption enabled after 1 clock cycle after FRAME asserted 31:28 Secondary bus arbiter preemption control RW 0010: Preemption enabled after 2 clock cycles after FRAME asserted 0011: Preemption enabled after 4 clock cycles after FRAME asserted 0100: Preemption enabled after 8 clock cycles after FRAME asserted 0101: Preemption enabled after 16 clock cycles after FRAME asserted 0110: Preemption enabled after 32 clock cycles after FRAME asserted 0111: Preemption enabled after 64 clock cycles after FRAME asserted
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15.2.33 P_SERR# EVENT DISABLE REGISTER - OFFSET 64h
Bit 0 Function Reserved Type RO Description Reserved. Returns 0 when read. Reset to 0 Controls bridge's ability to assert P_SERR# when it is unable to transfer any read data from the target after 224 attempts. 0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the command register is set. 1: P_SERR# is not asserted if this event occurs. Reset to 0 Controls bridge's ability to assert P_SERR# when it is unable to transfer delayed write data after 224 attempts. 2 Posted Write Non-Delivery RW 0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the command register is set 1: P_SERR# is not asserted if this event occurs Reset to 0 Controls bridge's ability to assert P_SERR# when it receives a target abort when attempting to deliver posted write data. 3 Target Abort During Posted Write RW 0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the command register is set 1: P_SERR# is not asserted if this event occurs Reset to 0 Controls bridge's ability to assert P_SERR# when it receives a master abort when attempting to deliver posted write data. 4 Master Abort On Posted Write RW 0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the command register is set 1: P_SERR# is not asserted if this event occurs Reset to 0 Controls bridge's ability to assert P_SERR# when it is unable to transfer delayed write data after 224 attempts. 5 Delayed Write Non-Delivery RW 0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the command register is set 1: P_SERR# is not asserted if this event occurs Reset to 0 Controls bridge's ability to assert P_SERR# when it is unable to transfer any read data from the target after 224 attempts. 6 Delayed Read - No Data From Target RW 0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the command register is set 1: P_SERR# is not asserted if this event occurs 7 Reserved RO Reset to 0 Reserved. Returns 0 when read. Reset to 0
1
Posted Write Parity Error
RW
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15.2.34 SECONDARY CLOCK CONTROL REGISTER - OFFSET 68h
Bit Function Type Description S_CLKOUT[0] (slot 0) Enable 00: 01: 10: 11: enable S_CLKOUT[0] enable S_CLKOUT[0] enable S_CLKOUT[0] disable S_CLKOUT[0] and driven LOW
1:0
S_CLKOUT[0] disable
RW
Reset to 00 S_CLKOUT[1] (slot 1) Enable 00: 01: 10: 11: enable S_CLKOUT[1] enable S_CLKOUT[1] enable S_CLKOUT[1] disable S_CLKOUT[1] and driven LOW
3:2
Clock 1 disable
RW
Reset to 00 S_CLKOUT[2] (slot 2) Enable 00: 01: 10: 11: enable S_CLKOUT[2] enable S_CLKOUT[2] enable S_CLKOUT[2] disable S_CLKOUT[2] and driven LOW
5:4
Clock 2 disable
RW
Reset to 00 S_CLKOUT[3] (slot 3) Enable 00: 01: 10: 11: enable S_CLKOUT[3] enable S_CLKOUT[3] enable S_CLKOUT[3] disable S_CLKOUT[3] and driven LOW
7:6
Clock 3 disable
RW
Reset to 00 S_CLKOUT[4] (device 1) clock enable 8 Clock 4 disable RW 0: enable S_CLKOUT[4] 1: disable S_CLKOUT[4] and driven LOW Reset to 0 Reserved. Reset to 1Fh Reserved. Reset to 00
13:9 15:14
Reserved Reserved
RO RO
15.2.35 P_SERR# STATUS REGISTER - OFFSET 68h
Bit 16 Function Address Parity Error Posted Write Data Parity Error Posted Write Non-delivery Target Abort during Posted Write Type RWC Description 1: Signal P_SERR# was asserted because an address parity error was detected on P or S bus. Reset to 0 1: Signal P_SERR# was asserted because a posted write data parity error was detected on the target bus. Reset to 0 1: Signal P_SERR# was asserted because the bridge was unable to deliver post memory write data to the target after 224 attempts. Reset to 0 1: Signal P_SERR# was asserted because the bridge received a target abort when delivering post memory write data. Reset to 0.
17
RWC
18
RWC
19
RWC
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Bit 20 Function Master Abort during Posted Write Delayed Write Non-delivery Delayed Read - No Data from Target Delayed Transaction Master Timeout Type RWC Description 1: Signal P_SERR# was asserted because the bridge received a master abort when attempting to deliver post memory write data Reset to 0. 1: Signal P_SERR# was asserted because the bridge was unable to deliver delayed write data after 224 attempts. Reset to 0 1: Signal P_SERR# was asserted because the bridge was unable to read any data from the target after 224 attempts. Reset to 0. 1: Signal P_SERR# was asserted because a master did not repeat a read or write transaction before master timeout. Reset to 0.
21
RWC
22
RWC
23
RWC
15.2.36 CLKRUN REGISTER - OFFSET 6Ch
Bit 24 Function Secondary Clock Stop Status Secondary CLKRUN Enable Type RO Description 0: Secondary clock not stopped 1: Secondary clock stopped. Reset to 0 0: Disable secondary CLKRUN 25 RW 1: Enable secondary CLKRUN Reset to 0 0: Allow primary clock to stop if secondary clock is stopped 26 Primary Clock Stop RW 1: Always keep primary clock running Reset to 0 0: Disable primary CLKRUN 27 Primary CLKRUN Enable RW 1: Enable primary CLKRUN Reset to 0 0: Stop the secondary clock only on request from the primary bus 28 CLKRUN mode Reserved RW 1: Stop the secondary clock whenever the secondary bus is idle and there are no requests from the primary bus Reset to 0 Reserved. Reset to 0.
31:29
RO
15.2.37 PORT OPTION REGISTER - OFFSET 74h
Bit 0 Function Reserved Type RO Description Reserved. Reset to 0
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Bit Function Type Description Controls bridge's detection mechanism for matching memory read retry cycles from the initiator on the primary interface 0: exact matching memory read retry cycles from initiator on the primary interface 1: alias MEMRL or MEMRM to MEMR for memory read retry cycles from the initiator on the primary interface Reset to 1 Controls bridge's detection mechanism for matching non-posted memory write retry cycles from the initiator on the primary interface Primary Memory Write Command Alias Enable 0: exact matching for non-posted memory read retry cycles from initiator on the primary interface 1: alias MEMWI to MEMW for non-posted memory read retry cycles from initiator on the primary interface Reset to 0 Controls bridge's detection mechanism for matching memory read retry cycles from the initiator on the secondary Secondary Memory Read Command Alias Enable 0: exact matching for memory read retry cycles from initiator on the secondary interface 1: alias MEMRL or MEMRM to MEMR for memory read retry cycles from initiator on the secondary interface Reset to 1 Controls bridge's detection mechanism for matching non-posted memory write retry cycles from the initiator on the primary interface Secondary Memory Write Command Alias Enable 0: exact matching for non-posted memory write retry cycles from initiator on the secondary interface 1: alias MEMWI to MEMW for non-posted memory write retry cycles from initiator on the secondary interface Reset to 0 Control's bridge's detection mechanism for matching memory read line/multiple cycles from the initiator on the primary interface Primary Memory Read Line/Multiple Alias Enable 0: exact matching for memory read line/multiple retry cycles from the initiator on the primary interface 1: alias MEMRL to MEMRM or MEMRM to MEMRL for memory read retry cycles from the initiator on the primary interface Reset to 1 Control's bridge's detection mechanism for matching memory read line/multiple cycles from the initiator on the secondary interface Secondary Memory Read Line/Multiple Alias Enable 0: exact matching for memory read line/multiple retry cycles from the initiator on the secondary interface 1: alias MEMRL to MEMRM or MEMRM to MEMRL for memory read retry cycles from the initiator on the secondary interface Reset to 1
1
Primary Memory Read Command Alias Enable
RW
2
RW
3
RW
4
RW
5
RW
6
RW
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Bit Function Type Description Controls bridge's detection mechanism for matching non-posted memory write and invalidate cycles from the initiator on the primary interface 0: When accepting MEMWI command at the primary interface, bridge converts MEMWI to MEMW command on the destination interface 1: When accepting MEMWI command at the primary interface, bridge does not convert MEMWI to MEMW command on the destination interface Reset to 0 Controls bridge's detection mechanism for matching non-posted memory write and invalidate cycles from the initiator on the secondary interface Secondary Memory Write and Invalidate Command Alias Disable 0: When accepting MEMWI command at the secondary interface, bridge converts MEMWI to MEMW command on the destination interface 1: When accepting MEMWI command at the secondary interface, bridge does not convert MEMWI to MEMW command on the destination interface Reset to 0 Controls bridge's ability to enable long requests for lock cycles 9 Enable Long Request 0: normal lock operation RW 1: enable long request for lock cycle Reset to 0 Control's bridge's ability to enable the secondary bus to hold requests longer. Enable Secondary To Hold Request Longer 0: internal secondary master will release REQ# after FRAME# assertion RW 1: internal secondary master will hold REQ# until there is no transactions pending in FIFO or until terminated by target Reset to 1 Control's bridge's ability to hold requests longer at the Primary Port. Enable Primary To Hold Request Longer 0: internal Primary master will release REQ# after FRAME# assertion RW 1: internal Primary master will hold REQ# until there is no transactions pending in FIFO or until terminated by target Reset to 1 Reserved. Returns 0 when read. Reset to 0.
7
Primary Memory Write and Invalidate Command Alias Disable
RW
8
RW
10
11
15:12
Reserved
RO
15.2.38 CAPABILITY ID REGISTER - OFFSET 80h
Bit 7:0 Function Enhanced Capabilities ID Type RO Description Read as 01h to indicate that these are power management enhanced capability registers.
15.2.39 NEXT ITEM POINTER REGISTER - OFFSET 80h
Bit 15:8 Function Next Item Pointer Type RO Description Read as 90h. Pointer points to the Hot Swap Capability Register.
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15.2.40 POWER MANAGEMENT CAPABILITIES REGISTER - OFFSET 80h
Bit 18:16 19 20 21 24:22 25 26 31:27 Function Power Management Revision PME# Clock Auxiliary Power Device Specific Initialization Reserved D1 Power State Support D2 Power State Support PME# Support Type RO RO RO RO RO RO RO RO Description Read as 010 to indicate the device is compliant to Revision 1.1 of PCI Power Management Interface Specifications. Read as 0 to indicate bridge does not support the PME# pin. Read as 0 to indicate bridge does not support the PME# pin or an auxiliary power source. Read as 0 to indicate bridge does not have device specific initialization requirements. Read as 0 Read as 1 to indicate bridge supports the D1 power management state. Read as 1 to indicate bridge supports the D2 power management state. Read as 0 to indicate bridge does not support the PME# pin.
15.2.41 POWER MANAGEMENT DATA REGISTER - OFFSET 84h
Bit Function Type Description Indicates the current power state of the bridge. If an unimplemented power state is written to this register, the bridge completes the write transaction, ignores the write data, and does not change the value of the field. Writing a value of D0 when the previous state was D3 cause a chip reset without asserting S_RESET# 00: D0 state 01: D1 state 10: D2 state 11: D3 state Reset to 0 Read as 0 Read as 0 as the bridge does not support the PME# pin. Read as 0 as the data register is not implemented. Read as 0 as the data register is not implemented. Read as 0 as the PME# pin is not implemented.
1:0
Power State
RW
7:2 8 12:9 14:13 15
Reserved PME# Enable Data Select Data Scale PME status
RO RO RW RO RO
15.2.42 PPB SUPPORT EXTENSIONS - OFFSET 84h
Bit 21:16 22 23 Function Reserved B2_B3 Support for D3HOT Bus Power / Clock Control Enable Type RO RO 1: when BPCEE pin is tied HIGH, driving secondary clock outputs LOW 0: when BPCCE pin is tied LOW RO 1: when BPCCE pin is tied HIGH Description Reserved. Returns 0 when read. Reset to 0 0: when BPCCE pin is tied LOW
15.2.43 DATA REGISTER - OFFSET 84h
Bit 31:24 Function Data Register Type RO Reset to 0 Description Data Register.
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15.2.44 PRIMARY MASTER TIMEOUT COUNTER REGISTER - OFFSET 88h
Bit 15:0 Function Primary Timeout Type RW Reset to 8000h. Description Primary timeout occurs after 215 PCI clocks.
15.2.45 SECONDARY MASTER TIMEOUT COUNTER REGISTER - OFFSET 88h
Bit 31:16 Function Secondary Timeout Type RW Reset to 8000h. Description Secondary timeout occurs after 215 PCI clocks.
15.2.46 CAPABILITY ID REGISTER - OFFSET 90h
Bit 7:0 Function Enhanced Capabilities ID Type RO Description Read as 06h to indicate that these are power management enhanced capability registers.
15.2.47 NEXT ITEM POINTER REGISTER - OFFSET 90h
Bit 15:8 Function Next Item Pointer Type RO Description Read as A0h. Pointer points to the VPD Capability Register.
15.2.48 HOT SWAP CAPABILITY STRUCTURE REGISTER - OFFSET 90h
Bit 16 Function Device Hide Active Type RW Description 0: Device is not hidden and PCI transactions are allowed during extraction state 1: Device is hidden and PCI transactions are not allowed during extraction state Reset to 0 0: Enable ENUM# signal 17 18 19 21:20 ENUM# Signal Mask Reserved LED On/Off Reserved RW RO RW RO 1: Mask ENUM# signal Reset to 0 Reserved. Reset to 0 0: LED off 1: LED on Reset to 1 Reserved. Reset to 00 Assertion of ENUM# based on a device being extracted 0: ENUM# asserted RWC 1: ENUM# not asserted Reset to 0
22
Extraction Status
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
Bit Function Type Description Assertion of ENUM# based on a device being inserted 0: ENUM# not asserted 23 Insertion Status RWC 1: ENUM# asserted Reset to 0
15.2.49 HOT SWAP SWITCH REGISTER - OFFSET 94h
Bit 0 7:1 Function Soft Hot Swap Extraction Switch Reserved Type RW RO 1: Board is in the inserted state Reserved. Reset to 0. Description 0: Pending extraction of board
15.2.50 VPD CAPABILITY ID REGISTER - OFFSET A0h
Bit 7:0 Function Enhanced Capabilities ID Type RO Description Read as 03h to indicate that these are VPD enhanced capability registers.
15.2.51 NEXT ITEM POINTER REGISTER - OFFSET A0h
Bit 15:8 Function Next Item Pointer Type RO Description Read as 0h. No other ECP registers.
15.2.52 VPD REGISTER - OFFSET A0h
Bit 17:16 23:18 30:24 Function Reserved VPD Address Reserved Type RO RW RO Description Read as 00 Contains the DWORD address that is used to generate read or write cycles to the VPD tables store in the EEPROM Read as 0 0: Performs VPD read command to VPD table at the location as specified in the VPD address. This bit is kept "0" and then set to "1" automatically after the EEPROM cycle is finished. 1: Performs VPD write command to VPD table at the location as specified in the VPD address. This bit is kept "1" and then set to "0" automatically after the EERPOM cycled is finished. Reset to 0
31
VPD Operation
RW
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
15.2.53 VPD DATA REGISTER - OFFSET A4h
Bit 31:0 Function VPD Data Type RW For writes, it places the current data in to the VPD table at the location as specified in the VPD address. Description For reads, it returns the last data read from the VPD table at the location as specified in the VPD address.
15.2.54 MISCELLANEOUS CONTROL REGISTER - OFFSET C0h
Bit Function Type Description 0: The following I/O addresses will not be claimed by the bridge and will not be forwarded on to the secondary bus 1: The following I/O addresses will be forwarded on to the secondary bus 8 Legacy ISA I/O Enable RW Game port: 0200h - 0207h FM: 0388h - 038bh Audio: 0220h - 0233h MIDI: 0330h - 0331h Reset to 0 Reserved. Reset to 0
15:9
Reserved
RO
15.2.55 GPIO CONTROL REGISTER - OFFSET C4h
Bit 7:0 8 9 Function Reserved GPIO[0] Input GPIO[0] Output Enable Type RO RO RW Description Reserved. Returns 00 when read. Reset to 00 State of GPIO[0] pin 0: GPIO[0] is an input pin 1: GPIO[0] is an output pin Reset to 0 Value of this bit will be output to GPIO[0] pin if GPIO[0] is configured as an output pin Reset to 0 Reserved State of GPIO[1] pin 0: GPIO[1] is an input pin 1: GPIO[1] is an output pin Reset to 0 Value of this bit will be output to GPIO[1] pin if GPIO[1] is configured as an output pin Reset to 0 Reserved State of GPIO[2] pin 0: GPIO[2] is an input pin 1: GPIO[2] is an output pin Reset to 0
10 11 12 13
GPIO[0] Output Register Reserved GPIO[1] Input GPIO[1] Output Enable
RW RO RO RW
14 15 16 17
GPIO[1] Output Register Reserved GPIO[2] Input GPIO[2] Output Enable
RW RO RO RW
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Bit 18 19 20 21 Function GPIO[2] Output Register Reserved GPIO[3] Input GPIO[3] Output Enable Type RW RO RO RW Description Value of this bit will be output to GPIO[2] pin if GPIO[2] is configured as an output pin Reset to 0 Reserved State of GPIO[3] pin 0: GPIO[3] is an input pin 1: GPIO[3] is an output pin Reset to 0 Value of this bit will be output to GPIO[3] pin if GPIO[3] is configured as an output pin Reset to 0 Reserved
22 23
GPIO[3] Output Register Reserved
RW RO
15.2.56 EEPROM CONTROL REGISTER - OFFSET C8h
Bit Function Type Description Starts the EEPROM read or write cycle During non-autoload periods, the bridge sets this bit to read/write data from/to the EEPROM. This bit is kept asserted until the command has been delivered to the EEPROM. Software must check to see if the Start bit becomes deasserted before issuing the next command. Reset to 0 Sends the command to the EEPROM 1 EEPROM Command 0: EEPROM read RW 1: EEPROM write Reset to 0 1: EEPROM acknowledge was not received during the EEPROM cycle. RO Reset to 0 0: EEPROM autoload was unsuccessful or is disabled RO 1: EEPROM autolad occurred successfully after RESET. Configuration registers were loaded with values in the EEPROM. Reset to 0 Returns 00 when read. Reset to 00 Determines the frequency of the EEPROM clock, which is derived from the primary clock 00: Reserved 01: PCLK / 256 (33MHz PCI operation) 10: PCLK / 128 11: Reserved Reset to 01
0
EEPROM Start
RW
2
EEPROM Error Status EEPROM Autoload Success Reserved
3
5:4
RO
7:6
EEPROM Clock Rate
RW
15.2.57 EEPROM ADDRESS REGISTER - OFFSET C8h
Bit 15:8 Function EEPROM Address Type RW Description Contains the EEPROM address
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
15.2.58 EEPROM DATA REGISTER - OFFSET C8h
Bit 31:16 Function EEPROM Data Type RW Description Contains the data to be written to the EEPROM. After completion of a read cycle, this register will contain the data from the EEPROM.
15.2.59 EEPROM TEST REGISTER - OFFSET CCh
Bit 31:30 Function Reserved EEPROM MSB/LSB Switch Type RO Description Returns 00 when read. Reset to 00 Controls the order of the data bit stream 0: data bit stream in Most Significant Bit order (Test purposes only) RO 1: data bit stream in Least Significant Bit order Reset to value of S_GNT#[2] pin during reset Controls the autoload speed 28 EEPROM Fast Autoload 0: Autoload in fast speed RO 1: Autoload in normal speed (Test purposes only) Reset to value of S_GNT#[1] pin during reset Allows the EEPROM autoload to be bypassed 27 EEPROM Autoload Bypass Enable 0: EEPROM autoload bypassed (Test purposes only) RO 1: EEPROM autoload not bypassed Reset to value of S_GNT#[0] pin during reset EEPROM autoload status 0: EEPROM autoload was unsuccessful or is disabled 26 EEPROM Autoload Status RO 1: EEPROM autolad occurred successfully after RESET. Configuration registers were loaded with values in the EEPROM. Reset to 0 Returns 0 when read. Reset to 0 0: EEPROM autoload enabled 1: EEPROM autoload disabled Reset to 1
29
25 24
Reserved EEPROM Autoload Disable
RO RO
15.2.60 SUBSYSTEM VENDOR ID REGISTER - OFFSET F0h
Bit 15:0 Function Subsystem Vendor ID Type RO Description Returns 12d8h when read. Can be changed by EEPROM autoload
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
15.2.61 SUBSYSTEM ID - OFFSET F0h
Bit 31:16 Function Subsystem ID Type RO Description Returns 8148h when read. Can be changed by EEPROM autoload.
16
ELECTRICAL AND TIMING SPECIFICATIONS
16.1 MAXIMUM RATINGS
(Above which the useful life may be impaired. For user guidelines not tested).
Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potentials (AVCC and VDD only] Voltage at Input Pins -65C to 150C 0C to 85C -0.3V to 3.6V -0.5V to 5.5V
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
16.2 DC SPECIFICATIONS
Symbol VDD, AVCC Vih Vil Vih Vil Vipu Iil Voh Vol Voh Vol Cin CCLK CIDSEL Lpin Parameter Supply Voltage Input HIGH Voltage Input LOW Voltage CMOS Input HIGH Voltage CMOS Input LOW Voltage Input Pull-up Voltage Input Leakage Current Output HIGH Voltage Output LOW Voltage CMOS Output HIGH Voltage CMOS Output LOW Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capacitance Pin Inductance Condition Min. 3 0.5 VDD -0.5 0.7 VDD -0.5 0.7 VDD 0 < Vin < VDD Iout = -500A Iout = 1500A Iout = -500A Iout = 1500A 0.9VDD 0.1 VDD VDD - 0.5 0.5 10 12 8 20 Max. 3.6 VDD + 0.5 0.3 VDD VDD + 0.5 0.3 VDD 10 Units V V V V V V A V V V V pF pF pF nH Notes 3, 4 3, 4 1, 4 1, 4 3 3 3 3 2 2 3 3 3 3
5
Notes: 1. CMOS Input pins: SCAN_EN, SCAN_TM# 2. PCI pins: P_AD[31:0], P_CBE[3:0], P_PAR, P_FRAME#, P_IRDY#, P_TRDY#, P_DEVSEL#, P_STOP#, P_LOCK#, P_IDSEL, P_PERR#, P_SERR#, P_REQ#, P_GNT#, P_RST, S_AD[31:0], S_CBE[3:0], S_PAR, S_FRAME#, S_IRDY#, S_TRDY#, S_DEVSEL#, S_STOP#, S_LOCK#, S_PERR#, S_SERR#, S_REQ#[3:0], S_GNT#[3:0], S_RST#, LOO, ENUM#. 3. VDD is in reference to the VDD of the input device.
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
16.3 AC SPECIFICATIONS
Figure 16-1
PCI Signal Timing Measurement Conditions
Symbol Tsu Tsu(ptp) Th Tval Tval(ptp) Ton Toff
Parameter Input setup time to CLK - bused signals 1,2,3 Input setup time to CLK - point-to-point 1,2,3 Input signal hold time from CLK 1,2 CLK to signal valid delay - bused signals 1,2,3 CLK to signal valid delay - point-to-point 1,2,3 Float to active delay 1,2 Active to float delay 1,2
66 MHz Min. Max. 3 5 0 2 6 2 6 2 14
33 MHz Min. Max. 7 10, 124 0 2 11 2 12 2 28
Units
ns
1. See Figure 16-1 PCI Signal Timing Measurement Conditions. 2. All primary interface signals are synchronized to P_CLK. All secondary interface signals are synchronized to S_CLKOUT. 3. Point-to-point signals are P_REQ#, S_REQ#[3:0], P_GNT#, S_GNT#[3:0], LOO, and ENUM#. Bused signals are P_AD, P_CBE#, P_PAR, P_PERR#, P_SERR#, P_FRAME#, P_IRDY#, P_TRDY#, P_LOCK#, P_DEVSEL#, P_STOP#, P_IDSEL, S_AD, S_CBE#, S_PAR, S_PERR#, S_SERR#, S_FRAME#, S_IRDY#, S_TRDY#, S_LOCK#, S_DEVSEL#, and S_STOP#. 4. REQ# signals have a setup of 10ns and GNT# signals have a setup of 12ns.
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16.4 66MHZ TIMING
Symbol TSKEW TDELAY TCYCLE THIGH TLOW Parameter SKEW among S_CLKOUT[9:0] DELAY between PCLK and S_CLKOUT[9:0] P_CLK, S_CLKOUT[9:0] cycle time P_CLK, S_CLKOUT[9:0] HIGH time P_CLK, S_CLKOUT[9:0] LOW time Condition 20pF load Min. 0 2.63 15 6 6 Max. 0.250 3.78 30 Units ns
16.5 33MHZ TIMING
Symbol TSKEW TDELAY TCYCLE THIGH TLOW Parameter SKEW among S_CLKOUT[9:0] DELAY between PCLK and S_CLKOUT[9:0] P_CLK, S_CLKOUT[9:0] cycle time P_CLK, S_CLKOUT[9:0] HIGH time P_CLK, S_CLKOUT[9:0] LOW time Condition 20pF load Min. 0 2.63 30 11 11 Max. 0.250 3.78 Units ns
16.6 POWER CONSUMPTION
Parameter Power Consumption at 66MHz Supply Current, ICC Typical 769 233 Units mW mA
Note: Data taken at 25C and 3.3V VCC
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PI7C8148A 2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
17
PACKAGE INFORMATION
17.1 160-PIN LFBGA PACKAGE OUTLINE
Figure 17-1 160-pin LFBGA package outline Thermal characteristics can be found on the web: http://www.pericom.com/packaging/mechanicals.php
17.2 PART NUMBER ORDERING INFORMATION
PART NUMBER PI7C8148ANJ PI7C8148ANJE SPEED 66 MHz 66 MHz PIN - PACKAGE 160-pin LFBGA 160-pin LFBGA (Pb-free & Green) TEMPERATURE 0C to 85C 0C to 85C
Page 90 of 90 JUNE 2004 - Revision 1.04

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